Senior ASIC Design Engineer

We are looking for a Sr. ASIC Design Engineer! NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have developed an outstanding team stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. What you'll be doing: You will document, implement, and deliver fully verified, high performance, area and power efficient RTL to achieve the design targets and specifications. Your responsibilities will include architecture and micro-architecture design, RTL design and synthesis, and logic and timing verification using pioneering CAD tools and semiconductor process technologies. In addition to the design role, you will participate in the verification of the design using sophisticated verification methodologies. You are expected to help define the verification scope and support the development of verification infrastructure. You will collaborate with several ASIC development teams and will need to communicate and coordinate with members of those teams, some of whom are in remote locations. What we need to see: A Bachelors or Masters Degree (or equivalent experience) 5+ years of relevant / meaningful work experience Proven hardware engineering background with a concentration in VLSI and Computer Architecture Expertise in Verilog, System Verilog or similar HDL. Proficient programming in Perl/Python

We are now looking for a Senior ASIC Design Engineer. NVIDIA is seeking ASIC Design Engineers to implement the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing! What you'll be doing: As a key member of the GPU Design team, you will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications. Analyze architectural trade-offs based on features, performance requirements and system limitations. Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. Collaborate and coordinate with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks. Work on a broad list of IPs such as GPU's work scheduler, time distribution system, interrupt controllers, and DMA engines. Architect features to help silicon debug and support post-silicon validation activities. What we need to see: Bachelors Degree or equivalent experience in Electrical Engineering, Computer Engineering or Computer Science. 8+ years of meaningful work experience. Experience in micro-architecture and RTL development (Verilog), focused on arbiters, scheduling, synchronization & bus protocols, interconnect networks and/or caches. Great understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis. Exposure to Digita

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. NVIDIA is seeking best-in-class ASIC Verification Engineers to verify the design and implementation of the world’s leading inference accelerator. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people around the globe. Their mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will help to build the high-performance processor elements that implement programmable compute and graphics functionality. What you'll be doing: As a key member of our ASIC Verification team, you will verify the design and implementation of inference accelerator You will be responsible for verification of the ASIC design, architecture, reference models and micro-architecture using advanced verification methodologies Understand the design and implementation of your unit, define the verification scope, develop the verification infrastructure and verify the correctness of the design Collaborate with architects, designers, and pre and post silicon verifi

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to join our dynamic and growing team. If you want to challenge yourself and be a part of something great, join us today! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing! More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to tackle, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence. What you'll be doing: You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc. Help in all aspects of physical design, such as driving timing convergence, timing constraints generation and management, and ECO generation and implementation. What we need to see: BS (or equivalent experience) in Electrical or Computer Engineering with 5&#43

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Principal ASIC Design Engineer About the Role At Micron, we transform how the world uses information to enrich life for all. As a global leader in memory and storage innovation, we develop technologies that accelerate intelligence and enable the next era of AI, ML, and advanced computing. Micron’s Interface Pathfinding team drives performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3–5 year technology horizon. A core part of that work is silicon-based validation of novel PHY solutions, and we are growing the team to execute. As the Principal ASIC Design Engineer , you will be the primary digital contributor on a deliberately small, senior team — united around the goal of carrying high-speed interface technologies from architecture to tape-out. The team’s analog and chip-level architecture is anchored by a deeply experienced analog custom design engineer; your role is to be the authoritative digital voice — owning RTL design and micro-architecture of the digital blocks, defining timing constraints, supporting verification, and serving as the key interface between the digital design and the analog and layout specialists who will carry the implementation through to silicon. On a test ASIC of this scope, the front-end digital work is the critical path, with contractor and layout support engaged as bandwidth demands warrant. What You’ll Own Digital Block Architecture & RTL Design Own the micro-architecture and RTL implement

InnoPhase Inc., DBA GreenWave Radios™, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Headquartered in San Diego, California, GreenWave Radios™ has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global R&D facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios™ continues to push the boundaries of radio technology and innovation. To learn more about GreenWave Radios™ and hear what our employees have to say, visit the GreenWave™ certification profile at GreatPlacetoWork.com or explore our Home - GreenWave Radios website. About the Role We’re looking for an experienced Principal Engineer/Manager to lead a small, high-impact team building next-generation cellular infrastructure radio Front Haul Gateway (FHGW) solutions in both FPGA and ASIC. You’ll own everything from architecture through production—defining features, authoring device specifications, and driving the design flow for high-performance programmable logic with embedded Linux-based wireless communications software. This is a senior technical leadership and management role with direct influence on our market-leading cellular infrastructure products, working hands-on alongside experts across design, verification, firmware, and system engineering. What You’ll Do Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project scheduling, and technical mentoring/oversight Own solution architecture end-to-end—taking marketing requirements and translating to product specifications through production-quality programmable logic design, verification and ha