Signal Integrity Hardware Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a highly skilled Physical Design Engineer to drive the critical Die-to-Die (D2D) Physical Implementation from RTL to GDSII. This role demands deep expertise in full physical design flow with a specific focus on closing high-speed D2D interfaces for multi-die/chiplet architectures. This role is remote role open to any location in the U.S. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned ASIC Physical Design Engineer with 5+ years at advanced nodes (7nm or below) and multiple successful tapeouts. Strong in full-chip implementation, comfortable owning blocks from RTL to GDSII across synthesis, floorplanning, place-and-route, CTS, and sign-off. Deeply familiar with high-speed interfaces (D2D, PCIe, HBM, SerDes) and the physical challenges that come with them (timing, signal integrity, power integrity). Detail-oriented and methodical with STA, constraints, and closure for complex, high-speed designs. A hands-on problem solver who enjoys collaborating across analog, digital, and full-chip teams to debug tough issues. What We Need Lead Die-to-Die (D2D) physical implementation and closure, taking high-spe

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a Mixed Signal IC Layout Design Engineer role involves full-custom physical layout of analog and mixed-signal integrated circuits, turning schematics into manufacturable layouts that meet performance, power, area, and reliability targets in advanced FinFET processes. The role focuses on high quality, high-speed analog/mixed-signal blocks and their integration into larger SoCs. This role is remote, based out of any in the United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are An experienced analog/mixed-signal IC layout engineer with strong full-custom layout background on high-speed blocks (PLLs, VCOs, ADCs, DACs, LDOs, comparators, clock generators, high-speed I/Os). Proficient with Synopsys Custom Compiler or Cadence Virtuoso for custom layout, and Synopsys ICV or Siemens Calibre for physical verification (DRC, LVS, ERC, DFM, Antenna). Deep experience in CMOS/FinFET nodes (ideally TSMC or Samsung 12nm–2nm) with delivered silicon and a strong grasp of EM/IR, ESD, and latch-up in mixed-signal layouts. Detail-oriented and organized, able to own complex blocks independently and collaborate effectively with cir

About the job Design the high-speed signal paths that let advanced AI compute systems perform at datacentre scale. As a Signal Integrity Engineer, you will shape the electrical performance of Graphcore hardware platforms. Your work will help 112Gbps and 224Gbps SERDES, DDR and processor interfaces operate within demanding system budgets. You will develop, extract and simulate PCB structures across production systems and test boards. You will define launches, via structures, transmission lines, stack-ups and low-loss materials for future designs. This role spans simulation, lab validation and practical design influence. You will work from concept through prototype bring-up, debug, validation and support for manufacture. The team and culture You will join the Hardware Engineering team, working closely with PCB, package substrate, system architecture and supplier teams. Work moves through simulation, design review, lab evidence and practical trade-offs. You will be expected to own signal integrity decisions across complex board and package interfaces. The team values careful analysis, pace and clear communication when problems need action. Decisions are made close to the engineering detail. You will challenge designs, guide constraints and help teams reach the best performance possible. What we’re looking for · Strong experience in high-speed digital circuit development, with deep signal and power integrity knowledge · Experience with high-frequency SERDES design and validation, including tens of GHz operation · Expertise using tools such as ANSYS SIWave, HFSS, Mentor HyperLynx or similar · Ability to design BGA and connector launches, via structures and transmission lines for GHz signals · Hands-on lab experience using VNAs, high-speed oscilloscopes and signal generators · Rigorous approach to design, debug and validation, with strong ownership and communication skills While we have outlined a set of requirements, we value transferable skills and diverse experiences.

About the job Design the high-speed signal paths that let advanced AI compute systems perform at datacentre scale. As a Signal Integrity Engineer, you will shape the electrical performance of Graphcore hardware platforms. Your work will help 112Gbps and 224Gbps SERDES, DDR and processor interfaces operate within demanding system budgets. You will develop, extract and simulate PCB structures across production systems and test boards. You will define launches, via structures, transmission lines, stack-ups and low-loss materials for future designs. This role spans simulation, lab validation and practical design influence. You will work from concept through prototype bring-up, debug, validation and support for manufacture. The team and culture You will join the Hardware Engineering team, working closely with PCB, package substrate, system architecture and supplier teams. Work moves through simulation, design review, lab evidence and practical trade-offs. You will be expected to own signal integrity decisions across complex board and package interfaces. The team values careful analysis, pace and clear communication when problems need action. Decisions are made close to the engineering detail. You will challenge designs, guide constraints and help teams reach the best performance possible. What we’re looking for · Strong experience in high-speed digital circuit development, with deep signal and power integrity knowledge · Experience with high-frequency SERDES design and validation, including tens of GHz operation · Expertise using tools such as ANSYS SIWave, HFSS, Mentor HyperLynx or similar · Ability to design BGA and connector launches, via structures and transmission lines for GHz signals · Hands-on lab experience using VNAs, high-speed oscilloscopes and signal generators · Rigorous approach to design, debug and validation, with strong ownership and communication skills While we have outlined a set of requirements, we value transferable skills and diverse experiences.

About the job Validate the memory and system interfaces that keep advanced AI compute reliable under real product conditions. As a Validation and Debug Engineer, you will help prove Graphcore silicon and platforms work across the conditions our customers need. You will build deep understanding of our devices, boards and system behaviour. You will create and execute validation and debug plans for new hardware platforms. Your focus will include LPDDR5-9600, slow-speed interfaces, PCB issues, power behaviour and signal integrity. This is hands-on lab work with real ownership. You will investigate failures, tune memory subsystems and turn complex findings into clear actions across hardware and firmware. The team and culture You will work with Architecture, Silicon Engineering, Hardware Engineering, Firmware, PCB design, power and signal integrity teams. Progress comes through lab evidence, practical judgement and clear debug reports. The team moves quickly because the problems are real and often complex. You will own bring-up activity, drive root cause analysis and keep issues moving across teams. Decisions are made close to the data. You will be expected to speak up, challenge assumptions and help teams choose the right corrective action. What we’re looking for · Strong hands-on hardware debug experience, including board bring-up and subsystem debug · Experience validating and tuning LPDDR memory subsystems, ideally including LPDDR5 · Ability to debug PCB, power, signal integrity and interface issues through to root cause · Knowledge of DDR training, timing optimisation, margin analysis, eye diagrams and stability validation · Confident use of lab instrumentation, including high-bandwidth oscilloscopes, BERT systems and VNA/TDR equipment · Ability to work independently, take responsibility and drive issue resolution across hardware and firmware teams While we have outlined a set of requirements, we value transferable skills and diverse experiences. If you meet most of

About the job Debug the high-speed interfaces that decide whether advanced AI systems perform in the real world. As a Validation and Debug Engineer, you will help prove Graphcore silicon and platforms work across real product conditions. You will build deep knowledge of our devices, boards and system behaviour. You will own hands-on validation and debug in the lab, focused on SerDes, PCIe Root Complex and Ethernet. Your work will help resolve complex issues across silicon, hardware, firmware and architecture teams. This role is for someone who enjoys getting close to the hardware. You will tune links, investigate failures and turn difficult lab findings into clear engineering decisions. The team and culture You will work closely with Architecture, Silicon Engineering, Hardware Engineering and Firmware. Progress comes through practical evidence, clear communication and fast problem solving. The team expects ownership without daily oversight. You will drive bring-up, debug issues and help teams reach decisions based on data. You will be trusted to speak up when something is unclear or risky. The best ideas can come from anyone close to the problem. What we’re looking for · Strong hands-on hardware validation experience, including board bring-up and subsystem debug · Experience validating and debugging Ethernet, PCIe Root Complex and SerDes systems · Confident use of lab instrumentation, including oscilloscopes, BERT systems, VNA/TDR equipment and PCIe protocol analysers · Ability to debug signal integrity, protocol-level and interface issues through to root cause · Experience with PCIe bring-up, LTSSM analysis, link training, equalization tuning and interoperability testing · Ability to work independently, take responsibility and drive issue resolution across teams While we have outlined a set of requirements, we value transferable skills and diverse experiences. If you meet most of our essential criteria, we encourage you to submit an application and showcase how you