Controller Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. You will join an inclusive, forward-thinking team dedicated to building technologies that power virtual reality, neural networks, and next‑generation computing. In this role, you will own design for test (DFT) solutions for complex high‑bandwidth memory (HBM) system‑on‑chip (SoC) base‑die designs. Your work will directly enable manufacturability, quality, and successful silicon bring‑up across current and future HBM generations. (LLM) Responsibilities will include, but are not limited to: Own SoC-level DFT structures and their implementation. This includes scan, memory built-in self-test (MBIST), logic built-in self-test (LBIST) where applicable, boundary scan (JTAG), and test access architectures for HBM base-die builds. Define and drive DFT architecture early in the design cycle, ensuring alignment with SoC integration, floorplanning, timing, power, and physical design requirements. Implement and integrate DFT logic at block, subsystem, and full‑chip levels while partnering closely with register‑transfer level (RTL) d

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE As Senior Product Manager for FlashArray Foundation, you will define and drive the core platform roadmap for Purity//FA, the operating system behind Everpure’s flagship enterprise storage appliance. You will bridge software and hardware co-design—owning controller enablement, flash media integration, high availability, and non-disruptive upgrades. Partnering closely with Engineering, Hardware, and the CTO office, you will turn complex storage protocols and hardware innovations into resilient, high-performance capabilities that maximize customer uptime and operational simplicity. WHAT YOU’LL DO Core OS & Platform Ownership : Drive the end-to-end vision and product requirements for Purity//FA core services, balancing high-availability failover, non-disruptive upgrades, and data reduction capabilities to consistently exceed enterprise SLAs. Protocol & Hardware Integration : Translate technical needs across storage protocols (FC, iSCSI, NVMe-oF, NVMe/TCP) and next-generation hardware into actionable product definitions that accelerate time-to-market for new storage innovations. Data-Driven Performance Optimization : Analyze system telemetry, benchmark metrics, and support trends to identify latency and throughput bottlenecks, converting findings into a prioritized, high-impact product backlog. Cross-Functional Execution : Partner with Platform PMs, Engineering, QA, and CTO architects to establish

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Join Micron’s SSD Hardware Architecture organization, where we develop the technologies that power next-generation storage solutions. We work across architecture, silicon, firmware, and product engineering teams to deliver high-performance SSD controllers that meet demanding standards for quality, reliability, and innovation. As a Staff SSD Hardware PCIe Engineer, you will play a key role in bringing advanced SSD controller technologies to life. This position offers the opportunity to lead PCIe subsystem validation, debug complex system-level challenges, and influence future product capabilities while collaborating with highly skilled engineering teams across the organization. Responsibilities: Develop hardware and system specifications from architectural and product requirements Lead PCIe bring-up, characterization, debugging, validation, and compliance activities for SSD controller SoCs Par

Titan Security is built on serving our clients and building careers – just like yours. We are trusted by some of the most well-known companies and properties in the country while remaining dedicated to building personalized security solutions that solve the needs of every customer we support. Named as a nationally recognized Top Workplace in 2024 and 2025 by USA Today, Titan's customized approach to security services will provide you with the opportunity to learn, grow and succeed. Our core values of being Unified, Transparent, Innovative, Committed and Accountable help us in providing unparalleled service and support in all that we do. If you are looking for a meaningful career, a culture of excellence, and the ability to make a difference, we want to talk to you! Staff Accountant Location: West Loop Office - Chicago, IL (on-site) Department: Finance & Accounting Reports To: Controller Position Summary The Staff Accountant plays a critical role in maintaining the integrity of the Company's financial records and supporting the monthly, quarterly, and annual close processes. This position is responsible for complex general ledger accounting, account reconciliations, payroll-related accounting, and internal control compliance for a large, multi-location security services organization employing approximately 13,000 employees nationwide. The ideal candidate is a detail-oriented accounting professional with strong analytical skills, experience working in high-volume environments, and the ability to effectively collaborate across departments including payroll, operations, human resources, and finance leadership. Essential Responsibilities Prepare and record monthly journal entries, accruals, prepaid expenses, and other general ledger transactions. Perform complex balance sheet account reconciliations and investigate variances. Support monthly, quarterly, and year-end financial close activities to ensure timely and accurate reporting. Reconcile cash and payroll-r

Job Details: Job Description: Intel Foundry Automation - Back End Automation Group is seeking a talented student to support our Automation Integrators in advancing manufacturing automation systems. Key Responsibilities: • Assist Automation Integrators with troubleshooting, system upgrades, user training, and root cause analysis to improve efficiency and reduce waste. • Enable Automation Integrators in designing, developing, testing, and debugging software for factory operations, wafer processing, and packaging across multiple software layers. • Support client-based Station Controller systems through validation, troubleshooting, and quality control. Collaborate with global cross-functional teams to drive automation projects and integrate machine learning and AI solutions as needed. Qualifications: Candidates must be currently pursuing a bachelor's degree in computer science, Data Science, Computer Engineering, or a related discipline. They should possess strong analytical, problem-solving, and communication skills, along with hands-on programming experience in languages such as Python, C, and C#. Knowledge of Agile software development methodologies and experience with manufacturing systems are highly desirable. Job Type: Student / Intern Shift: Shift 1 (Malaysia) Primary Location: Malaysia, Penang Additional Locations: Malaysia, Kulim Posti

We’re building a world of health around every individual — shaping a more connected, convenient and compassionate health experience. At CVS Health®, you’ll be surrounded by passionate colleagues who care deeply, innovate with purpose, hold ourselves accountable and prioritize safety and quality in everything we do. Join us and be part of something bigger – helping to simplify health care one person, one family and one community at a time. Position Summary CVS Health is seeking a highly skilled and visionary Sr. Manager to lead and manage our enterprise Cisco Application Centric Infrastructure (ACI) environment and the transition to Cisco Nexus Dashboard Fabric Controller (NDFC). This role sits within the Network Engineering team and is pivotal to driving the modernization and scalability of our next-generation data center fabric. This role will help set and drive the network technology strategy for ISTS, ensuring that ISTS delivers on our mission to transform technology and provide an agile, cost optimized and resilient set of network infrastructure services to meet the evolving needs of all the CVS Health lines of business. The ideal candidate will have experience supporting complex enterprise network environments and demonstrate deep expertise in Cisco ACI and NDFC technologies. As a strategic leader, you will be responsible for setting the direction, leading a team of engineers, and ensuring the operational integrity, performance, and evolution of our fabric-based data center architecture. This position will also mentor staff members in an effort to develop excellent enterprise networking skills. Key Responsibilities Lead the deployment, administration, and lifecycle management of the Cisco ACI environment Oversee the strategic transition to and ongoing management of the Cisco

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for a Rack Power Engineer with deep expertise in high-power conversion and distribution to design, qualify, and support power systems for AI supercomputers. You will own rack power solutions—including power shelves, AC/DC rectifiers, power supply units (PSUs), power management controllers (PMCs), and high-current distribution—from requirements and supplier development through deployment. You will also monitor fleet rack power health, lead debugging and root-cause investigations, and drive improvements into hardware, firmware, and qualification coverage. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own rack power architecture and requirements for high-power AI supercomputing systems, including power budgets, AC input interfaces, DC distribution, redundancy, efficiency, serviceability, and integration with data center infrastructure. Drive the design and supplier development of power shelves, rectifiers, PSUs, PMCs, busbars, connectors, and protection circuits. Review electrical designs and control behavior, and evaluate performance, cost, reliability, and availability trade-offs. Define and execute component, shelf, and rack qualification plans covering load transients, current sharing, hot-swap, startup and shutdown, redundancy failover, fault protection and recovery, thermal limits, and AC disturbances and ride-through

Leidos is seeking an experienced Program Analyst to support large information technology programs for our Utility Technologies Solutions team. In this role, you will provide program and project management support across a portfolio of IT projects supporting electric utility operations, technology modernization, and evolving grid initiatives for our utility client. You will help ensure projects remain organized, on track, and aligned with established governance and delivery standards while adhering to Leidos' Mission, Vision, and Values. The Program Analyst will support a Senior Program Manager/Portfolio Manager across a portfolio of utility IT projects, with a focus on project governance, document control, portfolio planning, reporting, and operational coordination. This role will work closely with Project Managers, IT Managers, Project Controllers, Schedulers, EPMO, and other business and technical stakeholders to help ensure projects meet established requirements and remain on track throughout the project lifecycle. The role will support stage-gate activities, maintain project and program documentation, coordinate portfolio information, assist with long-range planning, and help improve program processes and controls. The ideal candidate is highly organized, detail-oriented, proactive, and comfortable working across multiple projects and stakeholders in a fast-paced environment. Location: This position is based in South Plainfield, New Jersey, and requires onsite work three days per week, Tuesday through Thursday. Qualified candidates must reside within a reasonable commuting distance and be able to work onsite on these days. Salary: This position pays a salary in the range of $90,000 to $110,000 annually. Responsibilities: Provide day-to-day program man

NVIDIA's Silicon Co-design Group (SCG) sits at a rare intersection: we own the full product development lifecycle, from early architecture definition through silicon bringup to product release. Our ArchDev team is the hub for silicon and system-level feature development, driving tradeoff analysis, system integration, and POR alignment across the entire organization. If you want to see your work go from whiteboard to world-class silicon, this is where that happens. What You'll Be Doing: Architect and integrate system-level performance and power management features, controllers, and policies to optimize product efficiency across datacenter and client products . Build feature roadmaps to address low-power, low-noise, and performance-per-watt product needs through prototyping, use-case analysis, and cost/benefit trade-offs. Partner with architecture, ASIC, board/platform, software/firmware, and marketing teams to drive design decisions and debug complex issues. Track industry trends and market needs and translate them into forward-looking roadmaps that keep NVIDIA's products ahead of the curve. Lead debug efforts, develop workarounds, and support bringup , validation, manufacturing, and customer escalations. What We Need to See: <

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Design Engineer in the FLASH Group at Micron Technology, Inc., will be core technical individual contributor in design and validation of the on-chip controller and mixed signal circuitry in NAND FLASH chips. In this highly visible and challenging role, your responsibilities will include architecture development and product definition, detailed transistor level design, test plan, system integration and verification. Some RTL design and implementation of the controller hardware, design and development of firmware code for NAND internal operations and full-chip Verilog Validation. Successful candidates must have: Solid knowledge in Verilog language. Solid digital logic fundamentals. Basic understanding of analog circuits. An understanding and knowledge with mixed-mode design and validation. Through understanding of Design/Verification CAD tools such as ncsim, Design Compiler, Formality, PrimeTime, etc. Knowledge of TCL or PERL. Knowledge in non-volatile memory design (NAND in particular) is a strong plus. Using AI or AI proficiency is a plus About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performan

NVIDIA is now looking for a Senior Memory System Engineer to join our ASIC Memory Subsystem team! As a Senior Systems Engineer at NVIDIA, you'll join a group of hardworking engineers to develop and architect innovative Memory Solution for Tegra SoCs. In this position, you'll make a real impact in a multifaceted, technology-focused company. You will work with memory controller/PHY and Platform / System architect, Firmware, SI/PI, Memory suppliers to design and architect cutting edge, high speed and lower power memory technology for NVIDIA CPUs and SOCs. What You Will Be Doing: Analyze future DDR/LPDDR/HBM technologies to determine optimum performance, power, function and RAS in memory for Next generation SOC and Systems. Collaborate with ASIC Architects, Designers, Software and Firmware SW/FW teams to drive memory technology and associated requirements for memory controllers. Define Memory module, Package, and PCB layouts appropriate to the system workloads Debug and bring up memory evaluation / validation and failure issues on memory technology. Collaborate with DRAM suppliers and industry partners on to develop memory and memory related component technology. What We need to see: Bachelor's degree or master’s degree in Electrical Engineering, Computer Engineering (CE), or a related field (or equivalent experience) 10 years of proven track record in DRAM design, module design, or memory sub system design. Deep understanding and strong fundamental of memory design, features, ECC algorithm, SI and PI (Training algorithm) in DDR, LPDDR, and HBM. Strong understanding of memory sub system level interaction with Cache, Memory controller and PHY. Experience in the design, bring-up and validation for memory failure analysis Experience with Python, C/C

What You'll Do Physical scientist/engineer to take responsibility for testing and validation of novel hardware systems What We're Looking For Hands-on laboratory experience and the ability to work independently Familiarity with test and measurement equipment including: oscilloscopes, lock-in amplifiers, spectrum analyzers, PID controllers, etc. Proven diagnostic and troubleshooting skills, coupled with the drive to understand experimental results fully before proceeding Diligent record-keeping habits and facility with Python/Matlab/equivalent for data analysis and visualization Ability to work on-site (up to five days/week) in the San Francisco Bay Area Given the nature of the work, U.S. citizenship is required. Useful Experience Background in experimental physics, particularly in quantum or optical measurements Hands-on EE design and manufacturing experience: analog and digital electronics, board layout, soldering, etc. Excellent data presentation skills A desire to learn new skills outside your current area of expertise Proficiency using the latest AI tools to accelerate workflow

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The ASIC Logic Design Team plays a critical role in developing the custom silicon that powers Micron's industry-leading memory and storage solutions. Our team designs high-speed, high-performance ASICs and memory controller IP, collaborating closely with engineers across design, verification, validation, and product development to bring innovative technologies from concept to production. As a Digital Design Engineer Intern, you will work alongside experienced engineers to help design and develop next-generation ASIC solutions. This internship provides hands-on exposure to advanced semiconductor technologies and the complete ASIC development lifecycle, including digital, analog, and mixed-signal design. You will have the opportunity to contribute to meaningful projects while building technical expertise in a collaborative and innovative environment. What You Will Do Support the design and implementation of high-speed digital logic for tester ASICs and memory controller IP. Collaborate with cross-functional teams including Design Verification, Analog Design, Synthesis, Physical Design, and Lab Validation. Assist with integrating digital designs alongside custom analog circuitry and third-party IP solutions. Participate in design reviews and contribute to technical documentation. Present technical concepts and project updates to engineering teams. Explore and leverage AI-enabled design methodologies, including Generative AI and AI-assisted engineering workflows, t

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry. Micron’s High Bandwidth Memory (HBM) Design Verification team is responsible for ensuring the functionality, performance, and quality of next‑generation memory products that enable advanced computing applications. As a Senior Design Verification Engineer, you will collaborate closely with design, architecture, and product engineering teams to verify complex, high‑density DRAM circuits and deliver robust, production‑ready designs. This role combines deep technical verification expertise with cross‑functional collaboration in a global environment. You will be challenged by the complexity and difficulty of verifying high density memory chips (up to 32Gb) with huge scale of circuit capability (over 4M transistors), ultra-high speed designs, sophisticated functionality which includes next Generation DDR/LPDDR (ex: DDR5, LPDDR5) and advanced low power and power management technologies. You will be responsible to evaluate the functionality and performance of the Full-chip and block-level circuit designs using different verification tools, techniques, and strategies. In addition, you will also n

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron's ASIC Logic Design team develops next-generation ASICs and controller IP that enable industry-leading memory solutions. Working across advanced process technologies, the team collaborates with architecture, analog, verification, physical design, and validation engineers to deliver high-performance, production-ready silicon for future DRAM products. As an ASIC Digital Design Engineer, you will contribute to the design and development of RTL for next-generation DRAM memory controllers and subsystems. You will work in a collaborative engineering environment supporting design implementation, simulation, validation, and chip bring-up activities while leveraging AI-enabled tools to improve productivity and design quality. Responsibilities Design and develop RTL for DRAM memory controllers and subsystem components using SystemVerilog. Collaborate with analog, verification, physical design, validation, and other cross-functional teams to support successful product development. Develop and validate HDL models, support simulation and co-simulation activities, and analyze design functionality and performance. Support chip bring-up, debugging, and validation activities to identify and resolve design issues. Use scripting, automation, and AI-enabled tools to improve design workflows, productivity, and engineering efficiency. Minimum Qualifications 0-2 years of relevant experience through intern