Design Verification Engineer Intern in Jalisco

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a DRAM Design Engineering Group at Micron Technology, Inc. you will be responsible for translating schematics into layout used for the creation of fabrication reticules. You will be required to meet all engineering and process related criteria needed for an assigned DRAM product. You will organize and prioritize logistics and resource allocations to meet scheduled deadlines, and proactively develop methodologies for issue resolution. In this role you will work with Design and other engineering groups to apply multiple layout techniques for the design and verification of digital and analog circuits. You will be expected to understand various circuit design protocols, different fab processes, mask generation techniques, and tapeout processes and procedures. Responsibilities: Responsible for Design and development of IP layouts used in DRAM chips. Perform layout verification like LVS/DRC/EM, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/breakthroughs in multiple project environment. Contribute to effective project-management. Plan and detail your layout, presenting material for global teams to review Optimally connect with engineering teams in India, Japan the US, and other global teams to ensure the success of the layout project. Minimum Qualifica

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description We develop advanced memory technologies that transform how the world uses information to enrich life for all. As a Design Engineer, you will craft and optimize digital, analog, and memory circuits while collaborating with global design and verification teams. You will build solutions that improve quality, reliability, manufacturability, and product performance while continuing to learn and innovate in a global engineering environment! Responsibilities Design, develop, and optimize memory, logic, and analog circuits for new memory products. Perform circuit validation, parasitic modeling, reticle experiments, and tape-out revisions to drive performance and manufacturing efficiency . Lead layout activities including floorplanning, placement, routing, verification, modeling, and simulation using industry-standard tools. Collaborate across Product Engineering, Test, Probe, Process Integration, Assembly, and Marketing to solve technical challenges and support successful product execution. Drive innovation in future memory technologies while building design quality and standardization across global engineering teams. Minimum Qualifications Bachelor’s degree or equivalent experience in Electrical Engineering, Electronic Engineering, or a related field, with 10+ years of relevant industry experience; or a master’s degree with 7+ years; or a Ph.D. with 5+ years of relevant industry experienc

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, we innovate to transform how the world uses information to enrich life. For more than 40 years, we have developed advanced memory and semiconductor technologies that power innovation across industries worldwide. As a DRAM Engineering Group (DEG) Layout Designer at Micron Technology, Inc. you will be responsible for translating schematics into layout used for the creation of fabrication reticules. You will be required to meet all engineering and process related criteria needed for an assigned Dram product. You will organize and prioritize logistics and resource allocations to meet scheduled deadlines and proactively develop methodologies for issue resolution. In this role you will work with Design and other engineering groups to apply multiple layout techniques for the design and verification of digital and analog circuits. You will be expected to understand various circuit design protocols, different fab processes, mask generation techniques, and tape out processes and procedures. Our team vision is a continuing desire to develop your skills working in a Team across worldwide geographies! Enabling the creative career path you deserve with a collaborative environment and groundbreaking technology and growing upon your imagination and creativity. Responsibilities: Develop and optimize IP layouts for DRAM products while ensuring compliance with design, process, and reliability requirements. Perform physical verification activities including DRC, LVS, EM, quality reviews, and documentation

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are building innovative physical design capabilities that help bring advanced semiconductor products from concept to silicon. Our team collaborates across design, verification, and manufacturing disciplines to deliver high-quality solutions using leading-edge technologies. We value technical excellence, continuous learning, and a culture of teamwork and innovation. As a Physical Design Engineer, you will play a key role in driving semicustom physical implementation from netlist handoff through tapeout. You will work closely with cross-functional engineering teams to optimize design quality, achieve physical signoff, and support successful product delivery in advanced technology nodes. Responsibilities: Execute the semi-custom physical design flow from netlist handoff through physical verification and tapeout Develop and maintain floorplans, placement, routing, power distribution networks (PDN), and physical design constraints Perform DRC, LVS, parasitic extraction, and physical signoff activities Analyze and resolve timing, signal integrity, electromigration, IR drop, reliability, and manufacturability issues Partner with cross-functional teams to drive design closure, debug issues, and support tapeout readiness Minimum Qualifications: Bachelor's or Master's degree in Electrical Engineering or a related field Experience in VLSI physical design, semiconductor lay

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are building innovative physical design capabilities that help bring advanced semiconductor products from concept to silicon. Our team collaborates across design, verification, and manufacturing disciplines to deliver high-quality solutions using leading-edge technologies. We value technical excellence, continuous learning, and a culture of teamwork and innovation. As a Physical Design Engineer, you will play a key role in driving semicustom physical implementation from netlist handoff through tapeout. You will work closely with cross-functional engineering teams to optimize design quality, achieve physical signoff, and support successful product delivery in advanced technology nodes. Responsibilities: Execute the semi-custom physical design flow from netlist handoff through physical verification and tapeout Develop and maintain floorplans, placement, routing, power distribution networks (PDN), and physical design constraints Perform DRC, LVS, parasitic extraction, and physical signoff activities Analyze and resolve timing, signal integrity, electromigration, IR drop, reliability, and manufacturability issues Partner with cross-functional teams to drive design closure, debug issues, and support tapeout readiness Minimum Qualifications: Bachelor's or Master's degree in Electrical Engineering or a related field Experience in VLSI physical design, semiconductor lay

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Lead Principal Engineer, Layout Design at Micron, you will be at the forefront of developing groundbreaking memory solutions! This role is an outstanding opportunity to lead the physical implementation of modern DRAM and mixed-signal circuits, turning schematics and specifications into flawless, manufacturable layouts. You will collaborate with a world-class team of Circuit Designers, Verification Engineers, CAD/Methodology experts, Process Integrators, Product Engineers, Test/Probe specialists, Assembly professionals, and Marketing strategists. Together, we will drive cost, quality, reliability, time-to-market, and customer happiness through outstanding layout and build. Key Responsibilities Lead the layout build and physical realization of new memory products. Interpret device and circuit specifications to implement custom layout solutions meeting PPA (power, performance, area) and reliability targets. Develop hierarchical layouts for analog, digital, and memory-array-related circuitry using industry-standard EDA tools. Build block and top-level floorplans optimizing placement, routing resources, signal integrity, power delivery, and manufacturability. Optimize layout for critical metrics such as die size/area efficiency, matching, coupling/noise, and timing. Produce layout collateral and documentation for cross-team integration. Physical Verification and Tapeout Signoff Run and debug physical verification flows and ensure closure using indust

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has been at the forefront of innovation, delivering the world’s most advanced memory and semiconductor technologies. Our distributed team of engineers, scientists, and visionaries is developing groundbreaking solutions that redefine how the world uses information to enrich life for all. We are seeking a Layout Design Engineering Led to join Micron's organization in Guadalajara, Mexico. In this leadership role, you will guide a distributed team focused on developing complex analog, mixed‑signal, and custom layouts powering next‑generation AI and high‑performance computing solutions. Responsibilities Lead a team designing and developing critical analog, mixed‑signal, and custom block layouts, including support for full‑chip-level integration. Oversee layout verification activities, including LVS, DRC, Antenna checks, documentation, and quality reviews. Ensure timely and high‑quality delivery of block‑level layouts that meet all project requirements. Coordinate planning, area/time estimation, scheduling, task delegation, and execution for multiple concurrent projects. Mentor and guide layout engineers of all levels. Perform detailed reviews of sub‑block‑level layouts. Collaborate with global engineering teams to drive successful project execution and alignment across Micron’s worldwide footprint. Minimum Qualificatio

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate, and advance faster than ever. Micron’s MaskTech department is responsible for reticle data preparation and mask-related technologies that enable advanced semiconductor manufacturing. The team partners closely with Design, Process Integration, Mask Development, Scribe, Lithography, Tapeout Operations, Mask Shops, and Manufacturing Fabs to ensure successful tapeout execution and high-quality wafer patterning. As an Optical Proximity Correction (OPC) Engineer, you will process reticle design data through OPC to ensure designs are accurately transferred to silicon during photolithography. You will also develop and improve processes, automated verification methods, and systems that support tapeout operations while collaborating with global teams across the United States, Japan, and India to drive operational excellence and continuous improvement. Responsibilities Drive OPC job deck development, process flow execution, and recipe optimization to support production and R&D tapeouts. Collaborate with teams from multiple functions to develop new OPC flows, implement best-known methods (BKMs), and resolve manufacturing challenges. Analyze and troubleshoot OPC process issues, maintaining high-quality work to support a stable production environment. Develop automation, scripts, and process improvement

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has been at the forefront of innovation, delivering the world’s most advanced memory and semiconductor technologies. Our distributed team of engineers, scientists, and visionaries is developing groundbreaking solutions that redefine how the world uses information to enrich life for all. We are seeking a Layout Design Engineering Manager to join Micron’s High Bandwidth Memory (HBM) organization in Guadalajara, Mexico. In this leadership role, you will guide a distributed team focused on developing complex analog, mixed‑signal, and custom layouts powering next‑generation AI and high‑performance computing solutions. Responsibilities Manage a team responsible for crafting and developing critical layouts for analog circuits, mixed-signal components, and custom blocks, including support for full-chip-level integration. Oversee layout verification activities, including LVS, DRC, Antenna checks, documentation, and quality reviews. Ensure timely and high‑quality delivery of block‑level layouts that meet all project requirements. Coordinate planning, area/time estimation, scheduling, task delegation, and execution for multiple concurrent projects. Mentor and guide layout engineers of all levels. Perform detailed reviews of sub‑block‑level layouts. Collaborate with global engineering teams to drive successful project execution and alignment across Micron’s worldwide footprint. </

Design Layout Engineer — Jalisco, Mexico. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Micron Technology is a global leader in memory and storage solutions. As a Validation Engineer for DRAM Compute Products , you will be responsible for preparing, executing, and analyzing validation tests to ensure product functionality and reliability. You will work closely with cross-functional teams to identify and resolve silicon issues, expand validation coverage, and contribute to the development of new testing methodologies. Additionally, we require the use of AI tools and methodologies to improve our efficiency and schedule, resulting in overall savings Responsibilities Prepare validation tests and hardware setups for silicon testing. Execute validation tests and analyze results for accuracy and completeness. Categorize and report silicon issues efficiently. Investigate functionality and margin-related test results. Mitigate software and hardware limitations during validation by working with Design teams to assure quality. Report findings confidently to Design and support root cause analysis. Use Artificial Intelligence (AI) to develop tools, improve processes and shorten overall schedule Minimum Qualifications Bachelor’s degree in Electronics or Electrical Engineering or Master’s degree. 2–5 years of relevant experience. Strong circuit-level understanding, including simulation and debugging. Advanced proficiency in C, C&#43;&#43;, and/or Pyth

DRAM Design Engineer (Intern) — Jalisco, Mexico. Apply via Workday.

Analog Design Engineer — Jalisco, Mexico. Apply via Workday.

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Pathfinding Senior Design Layout Engineer — Jalisco, Mexico. Apply via Workday.