Dram Design Development Quality Engineer Jobs

NVIDIA is now looking for a Senior Memory System Engineer to join our ASIC Memory Subsystem team! As a Senior Systems Engineer at NVIDIA, you'll join a group of hardworking engineers to develop and architect innovative Memory Solution for Tegra SoCs. In this position, you'll make a real impact in a multifaceted, technology-focused company. You will work with memory controller/PHY and Platform / System architect, Firmware, SI/PI, Memory suppliers to design and architect cutting edge, high speed and lower power memory technology for NVIDIA CPUs and SOCs. What You Will Be Doing: Analyze future DDR/LPDDR/HBM technologies to determine optimum performance, power, function and RAS in memory for Next generation SOC and Systems. Collaborate with ASIC Architects, Designers, Software and Firmware SW/FW teams to drive memory technology and associated requirements for memory controllers. Define Memory module, Package, and PCB layouts appropriate to the system workloads Debug and bring up memory evaluation / validation and failure issues on memory technology. Collaborate with DRAM suppliers and industry partners on to develop memory and memory related component technology. What We need to see: Bachelor's degree or master’s degree in Electrical Engineering, Computer Engineering (CE), or a related field (or equivalent experience) 10 years of proven track record in DRAM design, module design, or memory sub system design. Deep understanding and strong fundamental of memory design, features, ECC algorithm, SI and PI (Training algorithm) in DDR, LPDDR, and HBM. Strong understanding of memory sub system level interaction with Cache, Memory controller and PHY. Experience in the design, bring-up and validation for memory failure analysis Experience with Python, C/C

DRAM Memory Design Engineer - Principal | MTS | SMTS — Boise, ID - Main Site. Apply via Workday.

Senior DRAM RTL design engineer — Hyderabad - Phoenix Aquila, India. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Design Technology Co-Optimization (DTCO) team works at the intersection of process technology, standard cell architecture, and design implementation to optimize power, performance, and area (PPA) for advanced memory products. The team collaborates closely with standard cell library, RTL, and physical design engineers to evaluate design tradeoffs and develop methodologies that improve silicon outcomes. As a DTCO Intern, you will gain hands-on experience assessing and optimizing PPA at the standard cell and logic block level. You will use industry-standard place-and-route tools and AI-enabled automation techniques to implement, benchmark, and optimize logic blocks while developing practical skills in physical design, timing closure, and design analysis. Responsibilities Implement standard cell logic blocks using industry-standard physical design tools, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization activities focused on PPA assessment. Analyze and benchmark power, performance, and area across standard cell libraries and logic block configurations, identifying opportunities for improvement. Perform static timing analysis (STA), investigate setup and hold timing violations, and support timing closure activities. Execute physical verification checks, including DRC, LVS, and IR-drop analysis, and assist with resolving design issues. Leverage Generative AI, AI Assistants, and Agentic AI solutions to automate data collection, reporting, comparison, and w

Design Engineer - DRAM Technology and Products — Boise, ID - Main Site. Apply via Workday.

Intern - DRAM IP Circuits Design Engineer — Boise, ID - Main Site. Apply via Workday.

DRAM Product Engineer - LPDDR Design for Test — Taichung - Fab 16, Taiwan. Apply via Workday.

DRAM Product Engineer – Mobile Design Validation and AI-Driven Optimization — Taichung - Fab 16, Taiwan. Apply via Workday.

Design Methodology – Senior / Staff DRAM Power Integrity Engineer — Hyderabad - Phoenix Aquila, India. Apply via Workday.

Design Methodology – Principal DRAM Power Integrity Engineer — Hyderabad - Phoenix Aquila, India. Apply via Workday.

Staff Design Verification Engineer, DRAM — Boise, ID - Main Site. Apply via Workday.

Staff Design Engineer, DRAM — Boise, ID - Main Site. Apply via Workday.

Principal Design Engineer, DRAM — Boise, ID - Main Site. Apply via Workday.

Principal Design Engineer, DRAM — Boise, ID - Main Site. Apply via Workday.

Semiconductor Design Engineer, DRAM — Jalisco, Mexico. Apply via Workday.