Dram Disability Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron has an opening for a Photolithography Engineer (Level 2 or 3) at our Boise, Idaho facility. This position is part of Micron’s Technology Development organization, where advanced ideas become manufacturable technologies. Our team works at the leading edge of memory innovation, partnering across design, integration, manufacturing, and equipment suppliers to enable the next generation of semiconductor devices. This is where curiosity, experimentation, and impact come together. As a Photolithography Engineer, you will play a key role in developing and integrating lithography processes that directly shape future memory technologies. You will work hands-on with tools, materials, layouts, and data, while leveraging Artificial Intelligence and other software, collaborating with global partners to move innovations from R&D into high-volume manufacturing. This role offers broad technical exposure and the opportunity to influence device performance, yield, and cost at scale. Responsibilities: Develop and integrate photolithography unit processes for advanced memory technologies Perform material evaluations, reticle, and layout development, OPC, overlay optimization, and process window analysis Drive yield improvement, failure analysis, and device performance optimization Partner with equipment vendors to evaluate tools and improve process capability Document processes, communicate results, and support technology transfer to manufacturing Leverage Artifi

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Design Technology Co-Optimization (DTCO) team works at the intersection of process technology, standard cell architecture, and design implementation to optimize power, performance, and area (PPA) for advanced memory products. The team collaborates closely with standard cell library, RTL, and physical design engineers to evaluate design tradeoffs and develop methodologies that improve silicon outcomes. As a DTCO Intern, you will gain hands-on experience assessing and optimizing PPA at the standard cell and logic block level. You will use industry-standard place-and-route tools and AI-enabled automation techniques to implement, benchmark, and optimize logic blocks while developing practical skills in physical design, timing closure, and design analysis. Responsibilities Implement standard cell logic blocks using industry-standard physical design tools, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization activities focused on PPA assessment. Analyze and benchmark power, performance, and area across standard cell libraries and logic block configurations, identifying opportunities for improvement. Perform static timing analysis (STA), investigate setup and hold timing violations, and support timing closure activities. Execute physical verification checks, including DRC, LVS, and IR-drop analysis, and assist with resolving design issues. Leverage Generative AI, AI Assistants, and Agentic AI solutions to automate data collection, reporting, comparison, and w

Engineer- DRAM, Advanced DRAM and EM Device/Cell Technology — Boise, ID - Main Site. Apply via Workday.

LPDDR DRAM Product Engineer — Taichung - Fab 16, Taiwan. Apply via Workday.

Sr DRAM Product Engineer — Manassas, VA - Fab 6. Apply via Workday.

MTS DRAM ASIC Architect — Bengaluru, India. Apply via Workday.

Senior DRAM System Engineer — Taichung - Fab 16, Taiwan. Apply via Workday.

Staff DRAM Design Engineer — Boise, ID - Main Site. Apply via Workday.

Advanced DRAM Process Integration Engineer — Boise, ID - Main Site. Apply via Workday.

Senior DRAM Design Engineer — Boise, ID - Main Site. Apply via Workday.

Senior DRAM RTL design engineer — Hyderabad - Phoenix Aquila, India. Apply via Workday.

Intern - DRAM Design Engineer — Boise, ID - Main Site. Apply via Workday.

Intern - DRAM Design Engineer — Boise, ID - Main Site. Apply via Workday.

Engineer- DRAM, Advanced DRAM and EM Device/Cell Technology — Boise, ID - Main Site. Apply via Workday.

Intern - DRAM IP Circuits Design Engineer — Boise, ID - Main Site. Apply via Workday.