Dram Hardware Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Overlay Strategy, Roadmap & Technical Leadership Own the overlay roadmap including bond overlay technologies. Serve as the technical authority for overlay, defining overlay specifications, error budgets, mark strategies, technical signoff criteria, and scaling requirements for future technology nodes. Develop innovative overlay solutions that enable advanced bonding while meeting performance, yield, manufacturability, and scaling objectives. Drive advancement of overlay metrology, automation, process control, modeling, and analytics capabilities in partnership with Process and Metrology teams. Apply advanced analytics, Artificial Intelligence, simulation, and experimental methodologies to accelerate learning, identify root causes, and improve overlay performance. Technology Development & Problem Solving Lead simulation and experimental process development activities, balancing modeling with hands-on characterization and technology development. Develop and maintain overlay error budgets, validation plans, experiments, and technical assessments that connect process behavior to device and integration requirements. Solve complex overlay challenges involving alignment, distortion, deformation, process interactions, and bonded wafers. Translate technical findings into actionable process improvements, technology decisions, and roadmap recommendations. <

Intern – Process Development Engineer, 3D DRAM Wet Etch — Boise, ID - Main Site. Apply via Workday.

Sr. Node Development Product Engineer - DRAM Technology — Boise, ID - Main Site. Apply via Workday.

New College Grad - Semiconductor Design Engineer, DRAM Products Group — Boise, ID - Main Site. Apply via Workday.

New College Grad - Design Engineer, DRAM Technology and Products — Boise, ID - Main Site. Apply via Workday.

Principal/Sr/Staff BEOL Engineer, DRAM PI — Hiroshima - Fab 15, Japan. Apply via Workday.

Principal / Senior / Engineer, E-characterization DRAM — Hiroshima - Fab 15, Japan. Apply via Workday.

New College Grad - Device Engineer, DRAM — Boise, ID - ID1. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking an experience high-speed high-speed IO/Clocking Design Engineering at a Principal/Sr Member of Technical Staff (SMTS) level to join our DRAM IP Design team and contribute to the development of critical high-speed IP circuits used across Micron’s DRAM memory products. In this role, you will be responsible for the architecture, design, development, optimization, verification, and technical support of these high-speed IPs. You will focus on equalization and bandwidth extension to push the limits of circuit and process performance, analyze IO impairments as well as clock jitter and duty cycle distortion, and assess their impact on DRAM system timing. You will also develop core strategy and implement effective engineering solutions to address these challenges. Relocation to Micron headquarter in Boise, Idaho is required for this position. Responsibilities: Define, innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products. Apply robust high-speed circuit design techniques and enhance critical performance evaluation, including timing and jitter sensitivity, of the IO data path and clock path at circuit and full-chip level. Develop accurate modeling, analysis and simulation methodology to capture key circuit performance metrics and their impact to product specifications at full-chip and system level. Work with Product Engineering and SI team to compare silicon performance with simulation resu

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a Principal/Member of Technical Staff (MTS) IO/Clock Design Engeer to join our DRAM IP Design team and contribute to the development of critical high-speed IP circuits used across Micron’s DRAM memory products. In this role, you will be responsible for the design, development, optimization, verification, and technical support of these high-speed IPs. You will focus on equalization and bandwidth extension to push the limits of circuit and process performance, analyze IO impairments as well as clock jitter and duty cycle distortion, and assess their impact on DRAM system timing. You will also develop and implement effective engineering solutions to address these challenges. Relocation to Micron headquarter in Boise, Idaho is required for this position. Responsibilities: Innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products. Apply robust high-speed circuit design techniques and enhance critical performance evaluation, including timing and jitter sensitivity, of the IO data path and clock path at circuit and full-chip level. Develop accurate modeling, analysis and simulation methodology to capture key circuit performance metrics and their impact to product specifications at full-chip and system level. Work with Product Engineering and SI team to compare silicon performance with simulation results and support correlation activities. Collaborate with process integration and transistor

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Interested in changing the landscape of artificial intelligence workloads? Join our team where we are building next-generation, high-bandwidth memory products. In Micron's High Bandwidth Memory Architecture organization, we partner closely with customers to deliver memory solutions purpose-built for emerging AI systems and applications. As a Senior Member of Technical Staff or Member of Technical Staff, DRAM Design Engineer in the next-generation HBM Architecture team, you will drive the architecture and optimization 3D-stacked, high-performance memories. Apply your knowledge to optimize DRAM designs and architectures for maximum performance, power, and area (PPA). This role is ideal for experienced DRAM designers who will identify, architect, design, and simulate next-generation architectures and memory features in collaboration with experts in stack architecture, memory systems architecture, and SoC microarchitecture. Responsibilities: Identify and develop novel DRAM circuit architectures that anticipate next-generation AI workload requirements, to unlock improvements in bandwidth and energy efficiency. Collaborate with peers to identify the highest-leverage DRAM circuit bottlenecks and define architectural hypotheses. Validate architectural hypotheses through schematic-level circuit design, SPICE simulation, and tradeoff analysis, establishing PPA feasibility. Partner with layout designers to conduct floorplanning studies. Colla

Sr. Engineer, Photo DRAM — Boise, ID - Main Site. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron’s DRAM Product Architecture Group partners across fabs, test, module, and system teams worldwide to deliver high-performance memory products. We work across geographies and functions to solve complex technical challenges, drive product innovation, and enable industry-leading DRAM solutions. Our team values collaboration, continuous learning, and making a measurable impact through engineering excellence. As a New College Graduate DRAM Yield & Quality Engineer, you will play a key role in monitoring and improving the health of Micron’s server DRAM products. Working with experienced engineers and cross-functional teams around the globe, you will analyze product and manufacturing data, investigate technical issues, and contribute to strategies that improve yield, quality, and performance throughout the product lifecycle. This is a highly visible role with direct impact on customer success and product reliability. Responsibilities Analyze silicon parametric, test, and manufacturing data to identify trends, resolve product issues, and support root cause investigations. Contribute to yield and quality improvement initiatives across new product introduction (NPI), qualification, ramp, and high-volume manufacturing. Collaborate with fab, test, module, quality, and operations teams to drive execution of product health objectives. Develop and maintain automation solutions to improve engineering efficiency, data analysis, and reporting. Apply AI, Agentic AI, and Generative AI tools to en

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description As an Engineering Execution Manager within Compute DRAM Product Engineering , you will lead engineering program execution for assigned DRAM products from pre-silicon readiness through qualification, production ramp, and transition to sustaining teams. This is an individual contributor leadership role, you will lead product execution across functional engineering teams through influence, technical judgment, and accountability. You will also collaborate across engineering and business organizations to build integrated plans, solve complex execution challenges, and deliver products that meet quality, yield, schedule, supply, and business requirements. Your work will have a direct impact on bringing innovative memory products to market! This technical leadership opportunity will allow you to develop broad product knowledge, strengthen your leadership skills across different functional groups, and learn across the semiconductor product lifecycle. Responsibilities Lead product execution from pre-silicon readiness through qualification and production ramp, building integrated schedules, dependencies, actions and decision points. Collaborate across Product Development, Design, Technology Development, Test, Package, Module, Quality, Manufacturing, Planning, and business teams to align technical and product achievements. Drive problem-solving for product risks and failures by facilitating issue triage, root-cause alignmen

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Staff Design Engineer is responsible for designing, simulating, and optimizing DRAM circuits while supporting the development of digital and analog circuitry used in advanced memory products. This role collaborates globally across design, verification, product engineering, test, probe, process integration, assembly, and marketing to ensure manufacturable, high‑quality, cost‑optimized solutions. The position drives innovation in future memory generations and contributes to silicon‑to‑system development in a dynamic engineering environment. Responsibilities Design digital, analog, and memory core circuits using CMOS logic and transistors, implementing device specifications from concept to solution. Utilize AI-Enabled tools to assist with schematic editing, data collection and layout floorplan. Create optimized floorplans for circuit placement, routing, power delivery, sense margins, array timing, and die size, including layout leadership. Conduct circuit simulations using FINESIM, HSPICE, and VERILOG; analyze power, performance, reliability, and parasitic impacts. Validate builds through reticle experiments, tape‑out revisions, and simulation‑to‑silicon correlation, identifying required schematic edits. Prepare and maintain design documentation while contributing to best‑known practices and departmental training. Collaborate with global build, verification, product engineering, test, probe, process integration, assembly, and marketing teams to ensure manufacturability and quality. <l