Eng Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. About Fab 4 Wet Process Operations Fab 4 Wet Process Operations supports the safe, efficient, and high-quality movement of wafers through the Wet Process area. Our team works closely with peer manufacturing areas, Process teams, Equipment teams, and many other organizations to supervise fab performance, manage production risks, optimize cycle time, and drive execution against move targets. Through real-time decision making and continuous improvement, we help ensure the fab meets customer and business commitments. Position Summary The Shift Manufacturing Engineer (ME) is responsible for driving daily fab performance within the assigned area. This role partners closely with Manufacturing Technicians, Shift Lead Engineers, Process Engineers, and Operations teams to achieve wafer move targets, optimize cycle time, respond to quality concerns, and maintain efficient workflow through the manufacturing line. Working on a 12-hour compressed workweek schedule, this position provides real-time operational leadership by identifying manufacturing constraints, supervising material flow, supporting production decisions, and driving actions needed to meet weekly wafer movement and wafer-on-hand objectives. Responsibilities: Supervise wafer movement performance by DID, process step, and operational targets. Identify manufacturing gaps, WIP imbalances, bottlenecks, and workflow disruptions. Develop and implement plans to close gaps and achieve weekly move and wafer-on-hand commitments.</l

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Manufacturing Development Engineering (MDE) Shift Engineer in Films, Metals, and Implant, you will play a critical role in supporting 24/7 process development for next-generation DRAM technologies. Operating on a 12-hour rotating shift schedule , you will serve as the primary off-hours technical resource for development activities, helping ensure uninterrupted execution of development experiments and rapid technology learning. This position operates in a dynamic development environment where process conditions, specifications, and experimental flows frequently evolve. You will apply sound engineering judgment to disposition development wafers, respond to process and equipment challenges, support experimental execution, and balance development priorities with operational requirements. You will also apply advanced analytics, automation, and AI-enabled technologies to improve engineering decisions, increase learning velocity, and support Micron's digital manufacturing initiatives. Responsibilities Serve as the primary off-hours technical resource for development activities, making decisions on wafer disposition, tool release, process deviations, execution risks, and development priorities. Partner with Films, Metals, and Implant Process Development, Process Integration, Equipment Development, Manufacturing, and Shift Operations teams to resolve process and equipment issues, remove output constraints, and support experimental processing. Apply Statistical Process Control (SPC), E3, Fault Detection (FD)

Experienced or Senior Interiors Payloads Support Engineer Company: The Boeing Company Boeing Commercial Airplanes Materials & Processes (BCA M&P) is seeking an Experienced or Senior Level Interiors Payloads Support Engineer (Level 3 or 4) to provide M&P engineering support to the 787 Program and Interiors Responsibility Center in South Carolina (IRCSC), located in North Charleston/Ladson, South Carolina. This role requires knowledge of Interiors materials and processes used in aerospace. These technologies include: composites, thermoplastics, thermosets, metals, fasteners, adhesives, sealants, organic and inorganic finishes, and corrosion principles. We seek detail-oriented, curious engineers who enjoy learning across Payloads/Interiors. Candidates with experience in composites, finishes, metals, or fasteners are especially encouraged to apply. Position Responsibilities: Support design engineers in material and process definition and selection of our Interiors components and flight deck structures Review drawings and specifications to ensure compliance with material and process requirements and objectives Understand engineering requirements and specifications to support material and process design consultation, production support, and fleet support Communicate with technical and non-technical personnel from multiple skill areas and functions to evaluate technical information and issues impacting design, production, and support of products, services, or other deliverables Continued on-the-job training to develop knowledge of Boeing systems, requirements, and material and process technology Develop tests to qualify new tools, equipment, mater

F/A-18 Senior Systems Engineer Company: The Boeing Company Boeing Defense, Space & Security (BDS) is seeking a Senior Systems Engineer to join the F/A-18 Systems Engineering Integration and Test (SEIT) Team in Berkeley, MO . The Senior Systems Engineer is responsible for leading cross-functional integration to drive engineering excellence in the execution of our F/A-18 software development activities. The individual selected for this role will be primarily focused on the Technical Integration role for Software Development and Advanced Systems activities. Position Responsibilities Ensure Engineering Excellence: Responsible for leading integration across multiple engineering and program teams to ensure safety, technical excellence, and product integrity. Drives adherence to Boeing and program processes, setting high standards for quality and performance Systems Engineering Approach: Ensure an integrated systems engineering approach. Take ownership to manage requirements and ensure full traceability. Manage the configuration of the integrated system to ensure dependencies are well understood. Responsible for ensuring comprehensive certification and verification activities, demonstrating a commitment to excellence Build Strategic Partnerships: Develop and nurture strong relationships with the United States Navy (USN), engineering functions, and program management. Leverage these partnerships to enhance collaboration and drive program success Manage Technical Baseline: Oversees the technical baseline, including mission systems configuration, technical performance measures, architecture diagrams, and Risk Identification and Opportunity (RIO) assessments. Foster

PWI R&D Writing Systems Engineer Description - A Writing Systems Engineer is an experience individual contributor responsible for owning system-level performance of industrial inkjet web presses , with a strong emphasis on hands-on engineering, on-press troubleshooting, and technical leadership . This role leads complex problem solving across ink, printhead, media, firmware, and mechanical systems, driving print quality, reliability, and robustness through a combination of deep systems thinking and direct experimentation . The specialist serves as a key decision-maker in resolving ambiguous, cross-functional issues and ensuring successful product delivery. Responsibilities Hands-on system ownership & advanced troubleshooting (Primary) Serve as the technical owner for system-level performance , including print quality, reliability, and production robustness Lead hands-on troubleshooting on industrial web presses , diagnosing complex print defects (banding, mottle, nozzle behavior, edge effects, etc.) Design and execute on-press experiments (DOEs) to isolate root causes and quantify system sensitivities Drive root cause analysis across subsystems (ink formulation, printhead, firmware, mechanics, media) and implement corrective actions Support press bring-up, ramp, customer escalations, and field issues , often in high-pressure situations requiring rapid, data-driven decisions Translate real-world press behavior into actionable engineering insights and design improvements System design & integration leadership Define and develop system-level solutions to optimize ink/media interactions, printhead performance, and image quality Lead integration of subsystems (ink, printheads, m

Reolink , a leader in intelligent visual technology for homes and businesses, was founded in 2009 by a group of engineers with a strong commitment to and passion for smarter security solutions. Our products are now trusted by millions of users across more than 110 countries and regions worldwide. Building on this trust, we continue expanding our presence and bringing our innovations to more markets around the globe. Reolink remains committed to delivering advanced, reliable, and user‑centric solutions that empower people to protect what matters most. AI Algorithms Engineer (PHD Holder Only) 5 Work Days Per Week Office Near Tai Seng MRT, Singapore Medical Benefits Provided Entitled to Yearly Bonus & Performance Bonus Job Requirements: PHD Holder in Computer Science, Applied Mathematics, Electrical Engineering, Pattern Recognition, Artificial Intelligence, Automatic Control, Operations Research, Biology, Physics / Quantum Computing, Neuroscience, Statistics or a related field. Familiar with common machine learning and deep learning algorithms and keeping track with the latest SOTA implementations. Strong programming skill in Python, C / C++, proficient in mathematical / statistical concepts and exceptional coding skills Hands-on experience with AI / ML frameworks be familiar such as Caffe, PyTorch, TensorFlow, MxNet etc. Have rich project experience in machine learning and deep learning, be familiar with common algorithm models, such as CNN, RNN, LSTM, Transformer, ViT, etc., and be able to improve and innovate models according to actual problems. Experience in familiar the design, parameter tuning and optimization methods of neural network models is a plus Experience in model compression and in the transplantation and optimization of deep learning forward inference on various platforms, including NPU / GPU / DSP / ARM on mobile platforms and CPU / GPU on server platforms is also a plus. Strong logical thinking and problem-solving ability, able to independen

Who We Are HP IQ is HP’s new AI innovation lab. Combining startup agility with HP’s global scale, we’re building intelligent technologies that redefine how the world works, creates, and collaborates. We’re assembling a diverse, world-class team—engineers, designers, researchers, and product minds—focused on creating an intelligent ecosystem across HP’s portfolio. Together, we’re developing intuitive, adaptive solutions that spark creativity, boost productivity, and make collaboration seamless. We create breakthrough solutions that make complex tasks feel effortless, teamwork more natural, and ideas more impactful—always with a human-centric mindset. By embedding AI advancements into every HP product and service, we’re expanding what’s possible for individuals, organisations, and the future of work. Join us as we reinvent work, so people everywhere can do their best work. About The Role HP IQ's Wireless Technology Team works cross-functionally with Electrical Engineering, Software, Mechanical Engineering, Product Design, Industrial Design, Program Management, and Operations to develop next-generation wearable and AI-connected products. As a Lead RF Systems & Desense Engineer, you will own the RF system architecture from concept through mass production. You will lead RF integration across Wi-Fi, Bluetooth, UWB, NFC and emerging wireless technologies while driving RF desense, coexistence, and wireless performance for highly integrated products. What You Might Do Lead RF system architecture and integration for wearable and mobile platforms. Own RF desense investigations and mitigation across the product lifecycle. Define RF specifications, link budgets, validation plans and performance targets. Lead coexistence strategy for Wi-Fi, Bluetooth, UWB, NFC and other radios. Partner with antenna, EE, FW, ME and silicon vendors to optimize total wireless performance. Perform CST and ADS simula

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE Powering the METCA AI & Sovereign Cloud Revolution As Everpure , we are transcending traditional storage to deliver the Enterprise Data Cloud - a unified architecture engineered to fuel the world’s most ambitious AI, Deep Learning, and HPC projects. The METCA region is a global epicenter for AI infrastructure investment, characterised by massive capital flowing into Tier-1 sovereign GPU clouds (CSPs, Neo-scalers) and enterprise AI factories. We are seeking a Battle-Trained, High-Conviction Hunting Systems Engineer (SE) to serve as our technical tip of the spear. This is not a passive, box-pushing relationship management role. You will partner aggressively with an Enterprise Account Executive to target, break into, and land the largest AI infrastructure projects in the market, displacing legacy architectures and securing net-new footprints. WHAT YOU'LL DO Execute High-Impact Hunting: Partner closely with Account Executives to actively map out and break into net-new enterprise accounts, sovereign GPU clouds, and high-performance computing clusters. Architect the AI Factory: Design high-performance, multi-tenant data pipelines. Move beyond basic storage architecture to design full-stack environments, optimising how data nodes interact within massive GPU fabrics. Drive Technical Consensus: Lead deep-dive architectural workshops with customer GPU cluster architects while simultaneously translating complex en

Location : Come and join us in Athens Being a Customer Care Executive is a role combining front office and back office duties for both drivers and passengers using Freenow by Lyft. You face users and turn them into the most passionate Freenow lovers, looking for unique and exciting ways to solve problems. You’ll be providing exceptional support, ensuring that issues occurring are resolved promptly and efficiently as part of our top-performing Customer Experience team. Your goal will be to ensure high-quality service to our clients and that our Real-Time Team runs smoothly and profitably. Shifts: 8h per day, 24h rotations; Monday to Sunday (incl. Bank Holidays), with 2 days off per week YOUR DAILY ADVENTURES WILL INCLUDE: Deliver high-quality support via calls, emails and messenger platforms Be a passionate advocate for riders and drivers while answering any questions that come your way Triage issues and escalate them when necessary Cooperate with other departments to assist inside projects and resolve technical issues Our Tools : Google Suite | Microsoft Office | Zendesk TO BE SUCCESSFUL IN THIS ROLE: Initial experience in customer support The ability to speak, read and write Italian and English, any other language is a plus - Please submit your application in English Good problem solving and active listening skills Ability to multitask and perform effectively under pressure Detail-oriented, proactive in process improvements BENEFITS & PERKS IN A NUTSHELL: Flexible working arrangements LinkedIn Learning Sabbatical & special leave policies WeRoad partnership Birthday, 24th + 31st December off Short term EU work policy Mobility Credit Health Insurance Employee assistance program Plus more local benefits depending on your work location! DIVERSITY, EQUITY & INCLUSION: Freenow is an equal opportunity employer and we consider qualified applicants regardless of race, religion, national origin, gender, gender identity, sexual or

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an Physical Design Engineer to lead cross-functional efforts to solve complex physical design challenges and develop end-to-end RTL-to-GDS methodologies across advanced nodes, with a strong focus on PPA and runtime improvements. The engineer will architect, integrate, and deploy AI/ML-driven solutions into production physical design flows, creating custom CAD tools and partnering with internal teams and EDA vendors to drive next-generation, ML-enabled capabilities. This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are BS in Electrical or Computer Engineering (or equivalent experience) with 5+ years in Physical Design CAD methodology at advanced nodes. Proven track record improving PPA and/or runtime on high-performance, low-power taped-out designs. Hands-on with industry-standard EDA tools (e.g., Fusion Compiler) across synthesis, P&R, STA, signoff, and hierarchical flows. Strong Python/Tcl and data skills, with interest or experience in ML frameworks (PyTorch, TensorFlow), and the ability to drive complex projects independent

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a highly technical Senior Staff/Principal Engineer to lead the porting and enablement of critical AI workloads. You will be a primary driver in migrating compute workloads to RISC-V architectures, ensuring our hardware is optimized for real-world application performance. The ideal candidate has a strong background in DevOps, workload porting, or application enablement . While this is an individual contributor role at its core, you will have the opportunity to grow and lead a small, specialized team over time as our workload migration efforts scale. This role is remote, based in the United States or Australia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A Technical Catalyst: You thrive on the challenge of driving AI hardware porting to RISC-V and making complex software stacks run efficiently on new hardware. Systems Expert: You possess deep knowledge of system software, compilers, or low-level OS internals. You are an expert in ARM or x86 environments and are ready to apply those skills to the RISC-V frontier. A Project Driver: You have the technical authority to lead the implementation of a compute migration to RISC-V through

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. You’ll lead physical verification closure (DRC, LVS, ERC, etc.), debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts. If you thrive in a fast-paced environment and enjoy solving complex challenges in cutting-edge silicon, we’d love to hear from you. This role is hybrid , based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure. A hands-on problem solver who excels at debugging and driving signoff through complex verification flows. A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces. A mentor and technical leader passionate about building efficient, manufacturable silicon. What We Need BS/MS in Electrical/Electronics Engineering (or related) with 7–14 years of hands-on CPU/IP/SoC physical verif

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Responsibilities and Duties We are seeking a highly skilled System Tests & Diagnostics Engineer to develop, extend, and integrate specialized silicon validation and diagnostics tools for next-generation AI SoCs. Unlike traditional validation roles focused on executing test plans, this position is responsible for developing the diagnostic software and stress tools that expose hardware failures, characterize silicon behavior, and improve platform observability throughout bring-up and validation. You will work closely with Arm engineers to understand and extend existing diagnostics technologies while developing Graphcore-specific capabilities for future AI hardware. Role Summary You will work with existing Arm-developed diagnostics technologies and extend them to support Graphcore's next-generation AI silicon. You will be responsible for developing system-level diagnostics and stress tools that integrate with an existing framework to detect data integrity, computational correctness, performance, and reliability issues across CPUs, AI accelerators, memory, storage, PCIe, firmware, BMC, and other platform components. Examples include silent data corruption (SDC) tests, power transient stress tools, and platform diagnostics, with opportunities to develop new diagnostics as future hardware capabilities evolve. This role requires close collaboration with hardware architects, firmware enginee

Staff -Power and Performance Validation Engineer About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Reporting to senior leadership within Architecture and Validation, the Power and Performance Validation Lead will drive validation strategy and execution for advanced AI compute silicon and systems. The role is responsible for leading power, thermal and performance validation activities across pre-silicon and post-silicon environments to ensure products meet efficiency, reliability and scalability expectations. This role requires strong technical expertise and collaboration across multiple engineering disciplines to deliver robust validation methodologies, scalable automation frameworks and actionable performance insights. The Team The Power and Performance Validation team sits within the Architecture and Validation organisation and is responsible for validating the performance, efficiency and thermal behaviour of Graphcore silicon and systems. The team supports the full product lifecycle, from early architectural modelling through to first silicon bring-up, characterization and production readiness. Engineers work closely with cross-functional teams globally to debu

Staff -Power and Performance Validation Engineer About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Reporting to senior leadership within Architecture and Validation, the Power and Performance Validation Lead will drive validation strategy and execution for advanced AI compute silicon and systems. The role is responsible for leading power, thermal and performance validation activities across pre-silicon and post-silicon environments to ensure products meet efficiency, reliability and scalability expectations. This role requires strong technical expertise and collaboration across multiple engineering disciplines to deliver robust validation methodologies, scalable automation frameworks and actionable performance insights. The Team The Power and Performance Validation team sits within the Architecture and Validation organisation and is responsible for validating the performance, efficiency and thermal behaviour of Graphcore silicon and systems. The team supports the full product lifecycle, from early architectural modelling through to first silicon bring-up, characterization and production readiness. Engineers work closely with cross-functional teams globally to debu