Fpga Developer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Summary Micron's Firmware & Product Test (FPT) team is hiring a Principal Test Development Engineer to lead front-end firmware validation for enterprise SSDs. In this role, you'll own verification strategy for NVMe front-end features, drive automation framework development, and serve as a technical authority for failure analysis and debug methodologies. You'll leverage AI-enabled tools and workflows to accelerate validation efficiency. You'll mentor engineers, define test coverage standards, and collaborate with firmware architects to influence testability decisions. The FPT team builds verification plans in Python, enforces NVMe and security protocol compliance, and executes white-box, grey-box, and black-box testing across simulation, FPGA, and prototype hardware environments. Responsibilities Lead design and execution of firmware verification strategies for NVMe front-end features (SMART, Trim, Get Log Page, OCP, Identify, Namespace Management) across multiple product lines. Own end-to-end test development lifecycle — from spec analysis and test planning through automation, execution, and coverage closure. Drive root-cause analysis for critical field and regression failures; establish systematic debug methodologies using coyote logs, protocol analyzers, and firmware traces. Architect and maintain scalable test automation frameworks that become organizational standards for firmware quality. Lead failure analysis efforts, correla

About Hark Hark is an artificial intelligence company building advanced, personalized intelligence. One that is proactive, multimodal, and capable of interacting with the world through speech, text, vision, and persistent memory. We're pairing that intelligence with next-generation hardware to create a universal interface between humans and machines. While today's AI largely operates through chat boxes and decade-old devices, Hark is focused on what comes next: agentic systems that interact naturally with people and the real world. To get there, we're developing multimodal models and next-generation AI hardware together - designed from the ground up as a single, unified interface for a new era of intelligent systems. About the Role The Embedded Software team owns the software running on Hark’s next generation of AI hardware, and we are looking for an Embedded BSP Engineer to join the team. You will own critical pieces of the firmware across the stack that powers Hark's consumer products, from board bring-up, vendor code integrations, to custom peripheral drivers and integrations, FPGA-based system integrations, and system power and performance improvements. Responsibilities Develop and maintain embedded firmware in C/C++ targeting ARM-based SoCs and microcontrollers Own BSP development, board bring up, peripheral drivers (SPI, I2C, UART, I2S etc.), and system integration Working closely with vendors on system integration and validation Working with Hardware and Software team to ensure our hardware are built and functioning to the specifications Optimize power consumption and thermal performance for always-on, battery-powered operation Debug complex hardware-software interactions using logic analyzers, oscilloscopes, and JTAG Requirements 5+ years of professional firmware or embedded systems development Strong proficiency in C and/or C++ in resource-constrained environments Experience with ARM Cortex-M or Cortex-A processors Hands-on experience wi

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The DRAM Systems & Architecture Lab researches next-generation memory architectures that enable future AI, machine learning, and high-performance computing systems. The team explores innovative memory technologies, system architectures, and hardware-software co-design approaches to improve performance, scalability, and efficiency for emerging AI workloads. As a Research Intern in the DRAM Systems & Architecture Lab, you will conduct research focused on next-generation memory systems for AI accelerators. You will investigate tiered memory architectures, analyze AI workload behavior, develop experimental prototypes, and evaluate architectural innovations across hardware, software, and system-level environments. This role offers the opportunity to contribute to research that may influence future product roadmaps, publications, and advanced memory system designs. Responsibilities Research and evaluate tiered memory architectures designed to improve performance and scalability for AI inference and large language model workloads. Develop experimental methodologies, models, simulations, and prototypes to analyze memory system performance, data movement, and workload behavior. Investigate memory hierarchy optimizations, data placement strategies, cache management, and memory migration mechanisms across AI computing systems. Perform quantitative analysis using hardware platforms, simulation environments, and FPGA-based prototypes to evaluate architectural trade-offs. Document research finding

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Senior Emulation Engineer Location: India - Remote Job Description: At EnCharge AI, we are building the next generation of AI compute silicon — purpose-built for high-performance, low-power, and scalable AI inference. As an Emulation Engineer, you will play a critical role in validating complex AI accelerator architectures on emulation platforms before tape-out. This position is ideal for someone passionate about bridging the gap between hardware and software in fast-paced, deep tech environments. Responsibilities: • Set up and maintain Siemens Veloce emulation and prototyping platforms • Adapt SoC designs for Emulation and Prototyping • Develop and debug emulation testbenches and system-level environments • Support pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-up and validation. • Collaborate with design and verification teams to isolate design issues and accelerate debug. • Optimize performance of the emulation workloads and reduce turnaround time. • Work with firmware/software teams to enable use of emulators for OS and driver testing. Required Background: • BS/MS/Ph.D. in EE, CS, or related field with 7+ years of SoC design experience. • Experience with emulation platforms (Veloce, Palladium, or ZeBu) and FPGA-based prototyping systems (proFPGA, HAPS, or Protium) • Experience with emula

Senior FPGA Design Engineer — Haifa. Apply via Workday.

ASIC/FPGA Design and Verification Engineer - (Lead, Senior, or Principal) — USA - Albuquerque, NM. Apply via Workday.

Lead ASIC - FPGA Design Engineer — IND - Bangalore, India. Apply via Workday.

InnoPhase Inc., DBA GreenWave Radios™, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Headquartered in San Diego, California, GreenWave Radios™ has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global R&D facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios™ continues to push the boundaries of radio technology and innovation. To learn more about GreenWave Radios™ and hear what our employees have to say, visit the GreenWave™ certification profile at GreatPlacetoWork.com or explore our Home - GreenWave Radios website. About the Role We’re looking for an experienced Principal Engineer/Manager to lead a small, high-impact team building next-generation cellular infrastructure radio Front Haul Gateway (FHGW) solutions in both FPGA and ASIC. You’ll own everything from architecture through production—defining features, authoring device specifications, and driving the design flow for high-performance programmable logic with embedded Linux-based wireless communications software. This is a senior technical leadership and management role with direct influence on our market-leading cellular infrastructure products, working hands-on alongside experts across design, verification, firmware, and system engineering. What You’ll Do Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project scheduling, and technical mentoring/oversight Own solution architecture end-to-end—taking marketing requirements and translating to product specifications through production-quality programmable logic design, verification and ha

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The DASG Architecture Lab and Customer Enablement Lab (CEL) teams provide the infrastructure, platforms, and technical expertise required to accelerate technology pathfinding, AI and system workload analysis, memory subsystem characterization, FPGA/LPDRAM prototyping, and customer enablement initiatives. These teams play a critical role in enabling architecture exploration, validation, and teamwork across engineering organizations and external partners. AI Efficiency and Usage is a must. AI proficiency or AI‑enabled ways of working where applicable. Agentic AI and Generative AI usage model is a must. Responsibilities Own the day-to-day bring-up, readiness, maintenance, and operational support of lab systems, racks, benches, test equipment, and reference platforms used by DASG Architecture Lab and Customer Enablement Lab teams. Deploy, configure, and maintain server, GPU, FPGA, client AI, mobile AI, analyzer, and environmental test equipment supporting workload characterization and technology pathfinding activities. Build and maintain stable, reproducible validation environments, including BIOS, BMC, firmware, operating systems, drivers, networking, remote access, and power and thermal configurations. Collaborate with architecture and validation teams to enable memory trace capture, workload analysis, DRAM replay, power and performance characterization, and data-driven engineering decisions. Develop and maintain operational processes for asset tracking, configuration management, equipme

What you’ll do Act as the in-house electrical lead for Midjourney Medical: own the electrical architecture of the scanner and the technical direction for all board-level design. Own complex board design end-to-end: architecture, schematic capture, layout (high-speed digital, analog/mixed-signal, power), DFM/DFT, fabrication and assembly vendor management, bring-up, and revision control. Write firmware for embedded targets (MCU/SoC): drivers, real-time control loops, safety-relevant logic, bootloaders, and field update paths. Audit and update HDL (FPGA) code for high-throughput data acquisition, timing/synchronization, triggering, and pre-processing of ultrasound and sensor data streams. Define electrical interfaces and data contracts with software, recon/ML and mechanical teams: timing budgets, clocking/sync, signal integrity, connectors/harnessing, and failure modes. Establish electrical engineering rigor: design reviews, schematic/layout review checklists, bring-up procedures, test fixtures, and documentation suitable for a regulated medical device program (DHF, traceability, change control). Mentor and grow the electrical function; select and manage external design partners where leverage is high. What we’re looking for Deep experience designing complex boards from blank page to stable revision, including high-speed digital and analog/mixed-signal domains. Strong schematic and layout skills (Altium/KiCad or equivalent) with real signal integrity, power integrity, grounding, and EMI/EMC instincts. Solid embedded firmware background in C/C++ (and Python for tooling): peripherals, DMA, interrupts, real-time constraints, and debugging on hardware. Practical HDL experience (VHDL/Verilog/SystemVerilog) for data acquisition, timing, and streaming interfaces. Track record of owning bring-up and debug on real hardware: scopes, logic analyzers, and disciplined root-cause analysis. Technical leadership: clear trade-offs, strong written documentation, and the ability to set

Role: Network Engineer Location: Gurgaon Graviton is a privately funded quantitative trading firm striving for excellence in financial markets' research. We are seeking a Network Engineer for our team in Gurgaon. Graviton trades across a multitude of asset classes and trading venues using a gamut of concepts and techniques ranging from time series analysis, filtering, classification, stochastic models, pattern recognition to statistical inference analysing terabytes of data to come up with ideas to identify pricing anomalies in financial markets. Key Responsibilities Design, deploy, operate, and troubleshoot low-latency network infrastructure used by trading firms. Manage connectivity to global stock exchanges, brokers, market-data providers, and ISPs. Build and maintain colocation infrastructure including routers, switches, Layer-1 devices (added advantage), structured cabling and cross connects. Configure and support Cisco Nexus, Arista and similar platform devices. Design and troubleshoot Layer 2 and Layer 3 networks including: VLANs, VRFs, BGP, OSPF, Static routing, PIM, IGMP, Multicast, SSM, ACLs and QoS. Troubleshoot packet loss, multicast issues, duplicate packets, IGMP/PIM and multicast/BGP routing. Monitor and optimize latency, jitter, packet loss, interface errors, congestion, and network performance. Work with ultra-low-latency technologies including: Cut-through switching, Layer-1 switches, FPGA-based network devices, Kernel-bypass networking, ExaNIC/Solarflare NICs, Hardware timestamping. Configure and troubleshoot PTP and clock synchronization infrastructure. Perform server and network equipment installation in exchange and third-party data centres. Manage rack layout, patching, cable optimization, optics, DACs, cross-connects, and inventory. Coordinate network changes with exchanges, telecom providers, brokers, vendors, and data-centre teams. Plan and execute production changes during approved maintenance windows. Perform pre-change validation, c

We’re looking for a hands-on Data Center Engineer to help us test, standardize, maintain, and improve server and network hardware for our globally distributed trading infrastructure. The role combines lab validation with hardware lifecycle operations: maintenance planning, coordinating onsite work with providers/contractors, ensuring quality execution and maintaining inventory. Travel will be required for deployments or complex troubleshooting. What You’ll be doing Test and compare server and networking hardware configurations (performance, stability, compatibility) Own hardware acceptance: burn-in checks, firmware/BIOS baselines, and “known-good” configs Plan and coordinate hardware maintenance and upgrades across sites (schedules, checklists, validation steps) Work together with onsite providers/contractors to execute installations and maintenance; review evidence and ensure quality Produce clear documentation: test results, approved SKUs, configuration standards, and maintenance runbooks Help troubleshoot hardware issues and support spares/RMA decisions Maintain inventory documentation What we look for in you: Solid understanding of server hardware basics (CPU/RAM/storage, NICs, firmware/BIOS, FPGA) and networking fundamentals Basic Linux skills for testing/benchmarking Accuracy and high level of attention to details Ability and willingness to solve problems in non standard way Structured troubleshooting mindset Comfortable coordinating work with external parties and driving tasks to completion. Able to document results and make recommendations based on data Willingness to travel internationally from time to time Nice-to-Have: Bare-metal fleet experience or lab/burn-in testing background Optics/cabling validation knowledge Experience with vendor/procurement coordination (RMAs, substitutions, lead times) Why should you join our team? Exciting challenges with ample opportunities for personal and professional growth A welcoming international team of highly qualified

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron's Firmware & Product Test (FPT) team is hiring a Staff Engineer to lead validation strategy for enterprise SSD firmware. In this role, you'll architect next-generation test frameworks, drive AI/ML-powered validation methodologies, and own end-to-end verification of complex NVMe front-end features across multiple product lines. You'll serve as a technical authority at the intersection of firmware validation and applied machine learning — shaping the strategic direction of our test infrastructure, mentoring engineers, and influencing firmware architecture decisions through deep validation insights. The FPT team builds verification plans in Python, enforces NVMe and security protocol compliance, and executes white-box, grey-box, and black-box testing across simulation, FPGA, and prototype hardware environments. Responsibilities Lead the design and execution of firmware verification strategies for customer specifications and NVMe protocols, owning validation of complex front-end features (SMART, Trim, Get Log Page, OCP) across multiple product lines. Architect scalable grey-box, white-box, and black-box test frameworks that become organizational standards for firmware quality. Drive root-cause analysis for critical field and regression failures; establish systematic debug methodologies and knowledge-sharing practices across the team. Own the test infrastructure roadmap — including automation frameworks, CI/CD integration, and reporting dashboards — and influence t