Hardware Operations Engineer Jobs

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We’re looking for a hands-on RTL Design Engineer to own the microarchitecture and RTL implementation of the Power Management Subsystem/Interrupt Controllers/AXI Interconnect/Cache Controller . You’ll collaborate with cross-functional teams—architecture, firmware, software, DV, and PD—to define, design, and optimize power management solutions for next-generation RISC-V/ARM-based SoCs. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels. During the interview process, you will beevaluated and offered a level that aligns with your experience, which may differ from the one in this posting. Who You Are 5–10 years of experience in ASIC/SOC/IP design, with hands-on experience in microarchitecture and RTL development Skilled in Verilog/SystemVerilog and comfortable working across design, debug, and analysis Design and develop microarchitectures for a set of highly configurable IPs Microarchitecture and RTL coding ensuring optimal performance, power, area Work with verification teams on assertions, test plans, debug, coverage, etc. Deep understanding of power management concepts—clocking, reset, DVFS, and low-power modes Familiar with RISC-V or ARM-based SoCs and standard bus protocols (AXI, AHB, APB, CHI) Awareness of functional safety (ISO 26262) practices in hardware design What We Need Abil

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an exceptional Senior-level Physical Design Engineer to drive top-level implementation of our complex AI and CPU System-on-Chip designs. You'll orchestrate cross-disciplinary collaboration, implementing sophisticated floorplans, power grids, and clock networks while ensuring design closure at the chip level. If you excel at managing the complexity of full-chip physical design and want to deliver next-generation AI hardware, we need your expertise. This role is hybrid , based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned physical design engineer who thrives on complex, full-chip implementation challenges. Expert at collaborating across disciplines, working effectively with architecture, RTL, and packaging teams. Passionate about optimizing chip-level implementations for power, performance, and area. Detail-oriented professional who drives design closure while maintaining quality and meeting aggressive schedules. What We Need 8+ years of top-level SOC physical design experience on complex, multi-million gate designs. Deep expertise in hierarchic

About Graphcore At Graphcore, we’re building the future of AI compute.We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence. Job Summary We are looking for an experienced System Level Test Engineer to join our Product Test and Diagnosis Department (PTD). In this role, you will lead the development and deployment of System Level Test (SLT) solutions for next-generation AI processors. Working closely with cross-functional teams, you will contribute to the design and implementation of SLT hardware, software, automation, and characterization solutions that support silicon bring-up, yield learning, manufacturing readiness, and production deployment. The ideal candidate will possess strong technical depth in semiconductor test and validation, a passion for solving complex engineering challenges, and a strong focus on product quality and manufacturability. The Team The Product Test and Diagnostics team’s role is to detect and manage hardware defects that arise from the manufacture and use of our products. This covers chips, boards and finished systems and takes place both in the manufacturing sites and in the field. Responsibilities and Duties Lead development and deployment of SLT hardware and software solutions supporting silicon bring-up, charac

About Graphcore At Graphcore, we’re building the future of AI compute.We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence. Job Summary We are looking for an experienced Silicon Test Engineer to join our Product Test and Diagnosis Department (PTD). This is a pivotal role and will involve building a team of engineers to develop System Level Test (SLT) capability within the company. Working closely with a cross-functional team you will implement SLT tests for a family of next generation AI Processors. The ideal candidate should have a focus on quality and demonstrate a good understanding of the importance of production test on the success of a product. T hey will have a proven Functional Test or ATE Test Engineering background, and will have a pragmatic, hands-on and flexible approach to a fast-changing environment. The Team The Product Test and Diagnostics team’s role is to detect and manage hardware defects that arise from the manufacture and use of our products. This covers chips, boards and finished systems and takes place both in the manufacturing sites and in the field. Responsibilities and Duties Managing a team of

1671 About the Role We are seeking a Senior Signal Integrity Engineer to develop, validate, and optimize high-speed signaling solutions across blade- and rack-level architectures for advanced compute platforms. This role sits at the intersection of silicon, package, interconnect, board, and system design , with a strong emphasis on hands-on measurement, simulation correlation, and cross-functional technical communication. Key Responsibilities End-to-end signal integrity analysis for blade- and rack-level system architectures. Analyze and optimize high-speed and low-speed I/O interfaces, including PCIe Gen4/5/6, Ethernet, DDR, SerDes, SPI , I2C, etc . and related interconnects. Perform time-domain and frequency-domain simulations using tools such as Ansys HFSS, Keysight ADS, Cadence Sigrity, CST, SPICE , or similar. Support hands-on lab validation using VNA, TDR, BERT, and high-speed oscilloscopes . Correlate simulation results with lab measurements to identify margin gaps, debug issues, and improve design methodology. Collaborate with silicon, package, board, connector, cable, and system design teams to optimize I/O channel performance. Work with interconnect vendors and ODMs to guide board layout, stack-ups, routing rules, and system design decisions. Review schematics, layouts, simulation results, and validation data for blade, backplane, and rack-level hardware. Prepare and communicate clear validation reports, measurement summaries, debug findings, and technical recommendations to internal teams, vendors, and senior technical stakeholders. Required Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field . Strong experience in signal integrity for high-speed digital systems. Hands-on measurement expertise using VNAs, TDRs, BERTs, and high-speed oscilloscopes . Experience measuring and analyzing S-parameters, impedance profiles, eye diagrams, jitter, timing margins, insertion loss, return loss, and cro

Job Summary Reporting to the Memory Validation leadership team, the Senior Silicon DDR/HBM Validation Engineer will be responsible for the bring-up, validation, characterization and debug of advanced memory subsystems used in next-generation AI compute platforms. The role will focus on DDR and HBM technologies, working closely with silicon design, firmware, characterization, platform and systems teams to ensure robust memory subsystem functionality, performance and reliability. The successful candidate will take ownership of significant validation activities, contribute to debug and root-cause analysis efforts, and help improve validation methodologies, automation and infrastructure. The Team The Memory Validation team sits within the Validation organisation and is responsible for the bring-up, validation, characterization and debug of memory subsystems across Graphcore silicon and platform products. The team supports DDR and HBM validation activities throughout the product lifecycle, from first silicon through production readiness. Engineers work closely with architecture, RTL, firmware, characterization, systems and platform teams to ensure memory technologies meet functionality, performance, reliability and performance objectives. Responsibilities and Duties Execute validation and bring-up activities for DDR and HBM memory subsystems Verify memory bring-up software, firmware and scripts against defined project requirements Debug firmware, hardware and system-level issues and contribute to root-cause analysis activities Analyse system logs, validation data and characterization results to identify failures and performance issues Perform PHY characterization and analog-level analysis during stress testing and validation activities Develop and execute functional, stress, performance and corner-case validation tests Perform signal integrity, voltage, frequency and timing measurements using laboratory instrumentation Char

About the Team DoorDash Labs, established in 2018, serves as the innovation hub for DoorDash, focusing on developing automation and robotics solutions to enhance last-mile logistics. The team's mission is to create technologies that support and augment human networks, aiming to improve efficiency for Dashers, merchants, and consumers alike. We’re ruthlessly focused on business impact. We are a highly senior team composed of former pioneers from a variety of different robotics industries. As of 2025, DoorDash has completed 10B lifetime deliveries. We’re focused on how to do the next 10B even better. About the Role We are seeking a highly motivated Senior Reliability & Test Engineer to join our team. This individual will play a key role in the development and validation of our unmanned platforms at the system and component levels. You will partner closely with EE, ME, and Autonomy teams to translate mission needs into robust, reliable hardware. The ideal candidate thrives in a fast-moving, cross-functional environment where reliability and test rigor determine program success. You will be hands-on in developing test methods and equipment to uncover failures before they happen in the field. You will partner closely with EE, ME, and Autonomy teams to translate mission needs into robust, reliable hardware. The ideal candidate thrives in a fast-moving, cross-functional environment where reliability and test rigor determine program success. You’re excited about this opportunity because you will… Architect and implement rigorous validation strategies, utilizing Python scripts for automation while leveraging CAD and shop tools to engineer bespoke test fixtures and hardware rigs. Oversee experimental execution across internal facilities and external laboratories, maintaining technical mastery over vibration tables, environmental chambers, DAQ systems, and ingress protection testing. Translate high-level vehicle reliability requirements into granula

Overview: The Insights product is a new offering for existing Guidepoint clients that offers teleconferences, in-person events and a call transcript library covering a wide of industries/topics that facilitate investment research. All content features experts from Guidepoint’s proprietary global network and is developed by former investment professionals (i.e. private equity/hedge fund) and sell-side equity research analysts. What You'll Do: Monitor a coverage universe of public companies within the technology sector by tracking earnings releases, investor presentations, SEC filings, sell-side research and industry news Create and moderate teleconferences on timely topics featuring an expert from Guidepoint’s network with the goal of producing actionable insights for clients Review teleconference transcripts to ensure quality of content High performers will be considered for full-time employment What You Have: Bachelor’s degree or Master’s degree Minimum 10 years of sell-side or buy-side analyst experience Must follow bottoms-up, fundamental approach to investment research focusing on individual companies Has covered Technology sector (Enterprise Software/SaaS, Internet (FANG etc) and/or Hardware/Semiconductors); candidates must be current on company/industry knowledge Ability to work in a fast-paced entrepreneurial environment Outgoing personality with the ability to speak with people at all professional levels Intellectual curiosity and desire to learn Effective time management and organizational skills Demonstrated ability to work both individually and as part of a team What We Offer: This is a full-time consultant role with the potential to convert to full time. The expected annual salary is $210,000 - $240,000. This rate may vary depending on job-related knowledge, skills, and experience, as well as geographic location. You will also be eligible for the following benefits: Friday happy hour, “Summer Fridays”, and free snacks and bevera

OVERVIEW: The Insights product is an offering for Guidepoint's institutional investment and corporate clients, now in its 9 th year, that offers teleconferences, surveys, in-person events, and AI-facilitated data and content. The teleconferences live in an online library portal, which covers a wide of industries/topics that enables our clients to make informed decisions. All content features experts from Guidepoint’s proprietary global network and is conceptualized and hosted by former investment professionals (i.e. hedge fund analysts), sell-side equity research analysts, and industry professionals. This is a hybrid position based in our New York City office. What you'll do: Build and lead a high-caliber research team: Recruit, develop, and manage a group of analysts producing differentiated, investor-grade insights across the technology, media and telecom (TMT) space, with full ownership over research quality, agenda-setting, and output. Own the research strategy and content roadmap: Define what gets covered and why—shaping expert calls, thematic work, and proprietary content aligned with real-time public equity investor demand Drive business growth and AI-enabled innovation: Partner with commercial and product teams to launch new research offerings, leveraging AI to scale insight generation, enhance workflows, and create differentiated products for institutional investor clients. What you have: Bachelor’s degree or Master’s degree Minimum 10 years of sell-side or buy-side analyst experience Must follow bottoms-up, fundamental approach to investment research focusing on individual companies Has covered all parts of the global TMT sector (Enterprise Software, Hardware & Semis and Consumer Internet); candidates must be current on company/industry knowledge Ability to work in a fast-paced entrepreneurial environment Outgoing personality with the ability to speak with people at all professional levels Intellectual curiosity and desire

SonicWall is a cybersecurity forerunner with more than 30 years of expertise and is recognized as a leading partner-first company, ensuring our partners and their customers are never alone in the fight against cybercrime. With the ability to build, scale and manage security across the cloud, hybrid and traditional environments in real-time, SonicWall provides relentless security against the most evasive cyberattacks across endless exposure points for increasingly remote, mobile and cloud-enabled users. With its own threat research center, SonicWall can quickly and economically provide purpose-built security solutions to enable any organization—enterprise, government agencies and SMBs—around the world. For more information, visit www.sonicwall.com or follow us on Twitter , LinkedIn , Facebook and Instagram . About the Role SonicWall is seeking a Software Dev Senior Engineer (Dataplane) with deep expertise in High Availability, Fast-Path Packet Processing, and Distributed Systems to architect and optimize the dataplane HA subsystem across SonicWall NGFW hardware and virtual firewalls — driving sub-millisecond session state synchronization, zero-packet-loss failover, and line-rate forwarding for IPsec, SSL-VPN, and TCP/UDP flows at 10G–100G+. Responsibilities Dataplane HA Architecture — Own fast-path HA engine design covering Active/Standby mirroring, Active/Active flow redistribution, and zero-drop VMAC/VIP failover. Stateful Session Mirroring — Build low-overhead dataplane sync for TCP/UDP 5-tuple tables, IPsec SA fast-path, SSL-VPN contexts, and L7 states across HA peers at line rate. Lock-Free Session Tables — Design NUMA-aware, lock-free (RCU/CAS/seqlock) session tables for multi-core pipelines sustaining tens of millions of concurrent sessions at sub-microsecond latency. High-Performance Sync Fabric — Engineer zero-copy ring buffer / DPDK mempool-based sync with prioritized queuing for IPsec/SSL-VPN state

SonicWall is a cybersecurity forerunner with more than 30 years of expertise and is recognized as a leading partner-first company, ensuring our partners and their customers are never alone in the fight against cybercrime. With the ability to build, scale and manage security across the cloud, hybrid and traditional environments in real-time, SonicWall provides relentless security against the most evasive cyberattacks across endless exposure points for increasingly remote, mobile and cloud-enabled users. With its own threat research center, SonicWall can quickly and economically provide purpose-built security solutions to enable any organization—enterprise, government agencies and SMBs—around the world. For more information, visit www.sonicwall.com or follow us on Twitter , LinkedIn , Facebook and Instagram . Senior Technical Program Manager – Software & Hardware What You’ll Do The Senior Technical Program Manager will work with globally distributed cross-functional teams of Product Management, Software, Hardware, QA, Sales, Marketing, and others to plan, execute, and launch new SonicWall software and network security products. You are responsible for managing the product lifecycle from concept to market launch while maintaining program schedules, budget, scope, and quality. This includes working with external labs and internal teams to achieve regulatory and other government/security certifications. This position reports to the Director of Program Management and is located in Pune, India. Who You Are You are an authority in the development and manufacturing of cybersecurity software and hardware appliances in the network security field. You are a leader who steers a cross functional team to achieve a common set of goals. You possess: Strong program management skills in the definition, planning, executi

About the Team OpenAI’s mission is to ensure that general-purpose artificial intelligence benefits all of humanity. The Design Systems team creates the foundations that help teams across OpenAI build coherent, high-quality experiences at scale. Accessibility is fundamental to that work. We’re building the shared standards, components, tools, and practices that make inclusive experiences the default across OpenAI’s products and platforms. About the Role In this role, you’ll lead OpenAI’s company-wide accessibility program from within Design Foundations. You’ll pair strategy and organizational influence with hands-on product design—advocating for disabled people, removing barriers across complete customer journeys, and establishing durable ownership throughout the company. This is an opportunity to define accessibility for a new generation of products spanning web, mobile, desktop, voice, AI, and hardware. You’ll help teams consider the many ways people perceive, understand, navigate, and interact with technology, going beyond minimum compliance to create experiences that are genuinely useful and inclusive. Working across design, engineering, research, product, go-to-market, and legal, you’ll make accessibility an expected part of product quality—not a final review or the responsibility of a single expert. This role is based in our San Francisco HQ. We offer relocation assistance to new employees. In this role you will: Define OpenAI’s accessibility strategy, roadmap, governance, priorities, and measures of progress. Design and ship accessible experiences while identifying systemic barriers across complete customer journeys. Build accessibility into our design system through inclusive components, tokens, interaction patterns, Figma libraries, documentation, and engineering guardrails. Center disabled people through participatory research, usability studies, and assistive-technology testing rather than relying solely on assumptions, simulations, or automated tools. Des

At Snowflake, we are powering the era of the agentic enterprise. To usher in this new era, we seek AI-native thinkers across every function who are energized by the opportunity to reinvent how they work. You don’t just use tools; you possess an innate curiosity, treating AI as a high-trust collaborator that is core to how you solve problems and accelerate your impact. We look for low-ego individuals who thrive in dynamic and fast-moving environments and move with an experimental mindset — who rapidly test emerging capabilities to discover simpler, more powerful ways to deliver results. At Snowflake, your role isn't just to execute a function, but to help redefine the future of how work gets done. We are looking for talented systems developers and researchers to join the Snowflake AI Research team and advance the state of the art in LLM inference systems and optimization . Our mission is to build the next generation of high-performance and intelligent inference systems . We optimize not only how fast and efficiently models run, but also how quickly inference systems can adapt to new models, architectures, hardware, and workloads. Our work spans the full inference stack—from distributed serving and runtime systems to GPU kernels and model-system co-design. We explore techniques such as adaptive parallelism, speculative and parallel decoding, disaggregated inference, scheduling and batching, KV-cache optimization, model swapping, quantization, and GPU kernel optimization to push the frontier of latency, throughput, scalability, and cost. Beyond optimizing individual models, we are building intelligent and adaptive inference systems that can automate performance optimization—rapidly profiling new models and workloads, identifying bottlenecks, selecting effective execution strategies, and adapting system configurations with minimal manual tuning. We embrace AI-native engineering , using AI not only as the workload we optimize, but also as a tool to accelerate system deve

Who we are About Stripe Stripe is a financial infrastructure platform for businesses. Millions of companies, from the world’s largest enterprises to the most ambitious startups, use Stripe to accept payments, grow their revenue, and accelerate new business opportunities. Our mission is to increase the GDP of the internet, and we have a staggering amount of work ahead. That means you have an unprecedented opportunity to put the global economy within everyone's reach while doing the most important work of your career. About the team Stripe Terminal helps businesses extend their online presence into the physical world. Our mission is to make it as easy for businesses to accept in-person payments as the Stripe API has made it for online payments. With Terminal, businesses can create flagship retail experiences, extend their websites to pop-up stores, or enable mobile point-of-sale payments at their next event. All of this is built on the Stripe Payments Platform, so businesses can maintain a single view of customers and sales across online and offline channels. Our hardware engineering team in Taiwan designs and builds the physical payment devices at the heart of that experience, including products such as the Stripe Reader S700 and Stripe Reader M2. We are expanding the team and seeking an experienced Senior Mechanical and Industrial Design Engineer who can own both the structural engineering and aesthetic form language of our next generation of payment terminals. This is a blended role. You will be equally comfortable driving design for manufacturability (DFM) for a plastic enclosure and sketching form concepts that express Stripe's design identity in hardware. What you'll do You will lead the industrial and mechanical design of next-generation Stripe Terminal payment devices, shaping their form, feel, usability, and structural performance from early concepts through mass production. You will partner with cross-functional teams and suppliers to deliver manufacturable,

Who We Are Nuro believes self-driving vehicles are the most immediate and profound opportunity for AI to drive positive change in the physical world. Safer streets, more time for what matters, and easier access to the world around us, that’s why we’re building a universal autonomy platform: self-driving for all roads and all rides. Founded in 2016, Nuro is a physical AI company developing Level 4 autonomous driving technology for a wide range of vehicles, use cases, and markets. Powered by the Nuro Driver™, our universal autonomy platform enables the global mobility ecosystem to deploy autonomy at scale, from robotaxis and logistics fleets to personal vehicles. With years of real-world deployment experience and a flexible, partner-led business model, Nuro is working toward a future where millions of autonomous vehicles powered by our technology help make everyday life safer, easier, and more connected. Nuro has raised over $2B in capital from Uber, NVIDIA, Google, Softbank, Fidelity, T. Rowe Price, and other leading investors. About the Team The Devices Platform team's mandate is to lay the foundation of Nuro's onboard software for our sensor and compute platform, including device drivers, inter-device protocols and pipelines, and device runtime APIs. Sensors and compute hardware are the eyes, ears, and brains of our self-driving robots. We are creating the hardware-agnostic platform to be used by the perception and autonomy SW stack, and to realize the full potential of our sensor and compute HW in reliability, quality, and performance. The projects we work on are high impact and high visibility within Nuro. This team is also responsible for working with internal stakeholders and external suppliers to define, evaluate, integrate the next generation HW platform for Nuro's products and to build the necessary tooling to assist continuous testing and validation. About the Work Design and develop sensor and compute systems for robotics Architect and/or deploy Nuro senso