Hbm 3d Power Delivery Network Engineer Jobs

ENGINEER, PDE HBM NPI — Taichung - Fab 16, Taiwan. Apply via Workday.

Principal DFT Engineer, HBM — 2 Locations. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of Micron’s High Bandwidth Memory (HBM) Design Architecture organization, where we push the limits of memory technology every day. Our team works across global, multicultural engineering groups to build next-generation HBM solutions that power AI and machine learning. We believe the best ideas come from collaboration, curiosity, and a shared drive to innovate! This role plays a critical part in ensuring the reliability of Micron’s most advanced DRAM and HBM products. As an ESD & Latch Up Engineer, you will shape protection strategies from early design through high-volume manufacturing, working hands-on with silicon, layout, and foundry partners. If you enjoy solving deep technical problems and influencing product robustness at scale, this role offers both impact and growth. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Define and own chip-level and IP-level ESD and latch up strategies for HBM DRAM, base die, I/O, TSVs, and die-to-die interfaces Establish ESD and latch up requirements, targets, and sign-off criteria aligned with JEDEC/ESDA standards Enable ESD protection circuits and latch up safe layout practices across designs and technologies Lead silicon validation, failure analysis, and correlation of pre-silicon assumptions to silicon results Act as the technical interface to foundries and partner closely with design, packaging, reliability, and product teams<

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As part of the Cloud Memory Business Unit (CMBU), this team advances Micron’s leadership in High Performance Memory solutions supporting Artificial Intelligence (AI), Machine Learning (ML), and High Performance Computing (HPC). The organization operates at the forefront of memory innovation, partnering closely with customers to enable next-generation computing capabilities. The Product Manager is responsible for defining and delivering the strategy for a High Performance Memory product portfolio. This role is critical to expanding Micron’s leadership in the HBM market by aligning product direction with customer needs, market trends, and emerging technologies, while driving cross-functional collaboration to deliver competitive solutions. Responsibilities Analyze emerging trends in AI hardware and evaluate their implications on high-performance memory architectures Define and drive product strategy and roadmap for high-performance memory products, ensuring alignment with market requirements and business goals Engage with customers, industry partners, and internal teams to gather insights on evolving AI/ML workloads and translate them into product requirements Assess the impact of next-generation AI workloads on future memory architectures and influence long-term product direction Support AI accelerator market analysis, including development of Total Addressable Market (TAM) and Serviceable Availab

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. As a Static Timing Analysis (STA) Engineer — you will be part of the Heterogeneous Integration Group (HIG), owning chip-level timing sign-off for next-generation die. You will work closely with RTL design, physical design, architecture, DFT, verification, and product teams to ensure timing integrity and drive timing closure across all modes and corners from initial design through tape-out. This is a hands-on senior technical role focused on chip-level STA ownership, constraint authoring, timing closure, methodology development, and pre-/post-silicon timing correlation. Key Responsibilities Responsibilities will include, but are not limited to: Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage and temperature conditions. Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration logic. Drive timing closure at block, sub

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron Technology is a global leader in memory and storage innovation, accelerating the transformation of information into intelligence. The High Bandwidth Memory (HBM) Heterogeneous Integration Group (HIG) develops advanced memory solutions that power next-generation Machine Learning (ML), Artificial Intelligence (AI), and high-performance computing applications. Our team brings together experts across design, validation, manufacturing, test, and quality to deliver industry-leading products through a highly collaborative and innovative environment. As a Design Validation Product Engineer, you will play a critical role in the development and validation of next-generation HBM products from design through qualification and high-volume manufacturing. This position provides the opportunity to work at the intersection of semiconductor design, silicon validation, hardware and software debugging, and data analysis while collaborating with multi-functional teams around the world. The level of responsibility will be aligned with a combination of education, experience, and demonstrated technical capabilities. Responsibilities Develop expertise in JEDEC HBM specifications, internal architecture documentation, and HBM design schematics and layouts. Perform silicon validation and characterization of HBM products using laboratory equipment, circuit simulations, debugging techniques, and data analysis. Collaborate closely with Product Engineering, Design, Manufacturing, Test, Quality, and other multi-functional teams to id

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron Technology is a global leader in memory and storage innovation, accelerating the transformation of information into intelligence. The High Bandwidth Memory (HBM) Heterogeneous Integration Group (HIG) develops advanced memory solutions that power next-generation Machine Learning (ML), Artificial Intelligence (AI), and high-performance computing applications. Our team brings together experts across design, validation, manufacturing, test, and quality to deliver industry-leading products through a highly collaborative and innovative environment. As a Design Validation Product Engineer, you will play a critical role in the development and validation of next-generation HBM products from design through qualification and high-volume manufacturing. This position provides the opportunity to work at the intersection of semiconductor design, silicon validation, hardware and software debugging, and data analysis while collaborating with multi-functional teams around the world. The level of responsibility will be aligned with a combination of education, experience, and demonstrated technical capabilities. Responsibilities Develop expertise in JEDEC HBM specifications, internal architecture documentation, and HBM design schematics and layouts. Perform silicon validation and characterization of HBM products using laboratory equipment, circuit simulations, debugging techniques, and data analysis. Collaborate closely with Product Engineering, Design, Manufacturing, Test, Quality, and other multi-functional teams to id

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron Technology, Inc., you will join a team responsible for bringing next-generation High Bandwidth Memory (HBM) products from design through high-volume manufacturing. This role plays a critical part in improving product reliability, accelerating production ramp, and enabling early time-to-market through advanced failure analysis. You will focus on analyzing failures from production test, internal qualification, and customer returns (RMA), using a combination of electrical, physical, and data-driven techniques to identify root causes related to fabrication or assembly processes. Key Responsibilities Perform electrical failure analysis and fault isolation using techniques such as emission microscopy, laser-based methods, and EOTPR. Analyze and model failure signatures from backend testing, qualification, and RMA data. Apply physical failure analysis (PFA) and de-processing techniques to isolate defects. Develop and maintain deep technical knowledge of CMOS/FinFET fabrication processes, device structures, and process integration. Generate clear, organized, and timely failure analysis reports, including root cause and corrective action insights. Collaborate multi-functionally with Product, Process, Assembly, Quality, and Management teams to communicate findings and drive resolution. Apply AI-assisted tools and workflows to analyze large datasets, identify failure patterns, and accelerate root-cause determination. Support flexible work sch

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Memory Systems Engineering team develops the digital and mixed-signal foundation that enables Micron's High Bandwidth Memory (HBM) products. The team works across architecture, PHY, design verification, DFT, and silicon validation functions to deliver innovative memory solutions that achieve demanding performance, power, and reliability targets. In this role, y ou'll receive mentorship from expert engineers while building expertise in sophisticated memory technologies. You will also contribute to the definition, implementation, integration, and validation of HBM base-die digital subsystems. You will collaborate with cross-disciplinary engineering groups to develop robust RTL solutions, support verification activities, and help ensure successful first-pass silicon execution. This position provides an opportunity to gain broad exposure to memory system design, silicon development methodologies, and AI-enabled engineering workflows. Responsibilities Define and implement digital micro-architecture for HBM base-die subsystems, including channel support logic, boot and initialization sequencing, training orchestration, configuration and status registers, telemetry, performance monitoring, and reliability features. Translate system requirements into timing, power, and area objectives while partnering with physical layer and system architects; develop and maintain interface specifications for bus protocols, clock-domain crossings, and reset architectures. Develop, integra

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry. Micron’s High Bandwidth Memory (HBM) Design Verification team is responsible for ensuring the functionality, performance, and quality of next‑generation memory products that enable advanced computing applications. As a Senior Design Verification Engineer, you will collaborate closely with design, architecture, and product engineering teams to verify complex, high‑density DRAM circuits and deliver robust, production‑ready designs. This role combines deep technical verification expertise with cross‑functional collaboration in a global environment. You will be challenged by the complexity and difficulty of verifying high density memory chips (up to 32Gb) with huge scale of circuit capability (over 4M transistors), ultra-high speed designs, sophisticated functionality which includes next Generation DDR/LPDDR (ex: DDR5, LPDDR5) and advanced low power and power management technologies. You will be responsible to evaluate the functionality and performance of the Full-chip and block-level circuit designs using different verification tools, techniques, and strategies. In addition, you will also n

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Job Description We are the HBM Design Architecture team within Micron’s HBM DRAM Engineering Group. We work at the intersection of design, technology, and manufacturing to deliver next‑generation HBM solutions that power AI and ML workloads worldwide. Our team thrives on deep technical collaboration, global partnerships, and solving problems that truly push memory technology forward! In this full‑time onsite role, you will provide critical technology support for the design and development of advanced HBM DRAM products. You will serve as a bridge between internal design teams, foundries, and technology development groups, helping translate advanced process capabilities into scalable, high‑performance architectures. Your work will directly impact performance, power efficiency, reliability, and long‑term HBM roadmap success. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. The responsibilities outlined below represent key areas of focus for this role and are intended to be illustrative rather than exhaustive. Candidates are expected to demonstrate relevant experience in at least three of the five focus areas outlined below. Job Responsibilities Foundry Interface and Technology Alignment Act as the primary technical interface between foundry partners and Micron design organizations. Drive closure of design-process gaps through collaborative engagement with foundry process teams. Influence foundry

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Key Responsibilities Validation Execution Lead end‑to‑end Validation Run execution in a high‑pressure, fast‑paced environment , ensuring on‑schedule starts/completions , risk‑aware re‑plans , and efficient IQP/ETV material usage . Own time‑bound data crunching pipelines (automated log parsing, metrics aggregation, anomaly ranking) and deliver decision‑ready summary reports and sightings by agreed Cycle Time . Guarantee coverage completeness across MBIST and Native flows; drive Hot/Cold corners , TSV screen/AQLK , async timing boundary coverage, and evidence‑backed closure . Platform Leadership Develop and debug test programs on SM3/Cobra and Advantest V93K ; enforce code quality, reviews, and release discipline. Align hardware configs ( handler, socket, loadboard, probe card ) to test intent and throughput targets. Advanced Analysis, Verilog Simulation & Automation Perform power/thermal characterization ; correlate IDD/thermal data with performance/reliability; author recommendations for content changes and silicon fixes. Architect and execute

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Responsibilities Validation Execution Assist in executing Validation Runs on IQP/ETV materials under defined timelines, ensuring coverage completeness across MBIST and Native Mode flows. Support time-bound data crunching (log parsing, statistical summaries) and contribute to summary report preparation. Platform & Test Program Support Operate and debug programs on SM3/Cobra (MBIST) and Advantest V93K (Native) . Assist in hardware readiness: handler, socket, loadboard, and probe card setup. Technical Analysis & Simulation Validate high-speed I/O (>11 Gbps) and assist with eye diagram and signal integrity checks. Support Verilog simulation tasks (testbench execution, waveform review) to reproduce sightings and validate fixes. Data & Automation Develop basic scripts in Python for log parsing and data visualization. Maintain documentation in Confluence/Jira and version control in Git/Perforce. Debug & Collaboration Participate

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description We are the HBM Design Architecture team within Micron’s HBM DRAM Engineering Group. We work at the intersection of design, technology, and manufacturing to deliver next‑generation HBM solutions that power AI and ML workloads worldwide. Our team thrives on deep technical collaboration, global partnerships, and solving problems that truly push memory technology forward! In this full‑time onsite role, you will provide critical technology support for the design and development of advanced HBM DRAM products. You will serve as a bridge between internal design teams, foundries, and technology development groups, helping translate advanced process capabilities into scalable, high‑performance architectures. Your work will directly impact performance, power efficiency, reliability, and long‑term HBM roadmap success. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Job Description The responsibilities outlined below represent key areas of focus for this role and are intended to be illustrative rather than exhaustive. Candidates are expected to demonstrate proven experience in at least three of the five focus areas outlined below. Foundry Interface and Technology Alignment Act as the primary technical interface between foundry partners and Micron design organizations. Drive closure of design-process gaps through collaborative engagement with foundry process teams. Influence foundr

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an SoC Physical Design Senior Manager, HBM in the Heterogeneous Integration Group (HIG), you will lead a team of physical design and physical verification engineers responsible for implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tapeout. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. Key Responsibilities Recruit, develop, and mentor a team of physical design engineers delivering HBM base die products. Plan project resourcing requirements and timelines. Prioritize resources across projects and individual assignments to meet aggressive product delivery schedules. Drive physical implementation for SoC blocks and/or top-level including floorplanning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Collaborate with design and integration teams to ensure clean implementation of clocking/reset strategy, power architecture, and SoC integration requirements. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust