Hbm Advanced Package Process Equipment Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As a Probe Integration Engineer at Micron Technology, Inc. within Test Solutions Engineering Department Key Equipment Group (KEG); you will have responsibilities for developing, deploying, and supporting Wafer Probe Equipment and Processes used in our manufacturing global locations with an emphasis on HBM (High Bandwidth Memory). The successful candidate will spend much of their time working on company-wide initiatives promoting greater quality, efficiency, and standardization of Probe operations together with enabling Probe roadmap technologies. A typical day in this position allows candidates to be creative and innovative in the deployment of first-of-a-kind solutions that solve complex problems. Responsibilities and Tasks: Responsibilities for this role will include, but are not limited to, the following: Deploy first-of-a-kind equipment and process capabilities through evaluations of Wafer Probers, Testers & Probe Cards Collaborate with global teams to establish and implement the best-known method probe processes globally. Engage equipment suppliers & vendors to address issues of quality, performance, and change management. Establish manufacturing metrics to drive continuous improvement of equip

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As a Cost Engineer within MSH/ MSB Lean Manufacturing, you will be responsible for driving cost efficiency across High Bandwidth Memory (HBM), Component Assembly and Test, and SSD operations. You will collaborate with cross-functional teams to identify , implement, and govern cost improvement initiatives, ensuring alignment with site and network-wide financial goals. Main Responsibilities Manage and introduce cost improvement programs across manufacturing operations High-bandwidth Memory (HBM), Multi-Chip Packages (MCP ) and Low Power DRAM (LPDRAM) Component Assembly/Test/SSD . Perform month-end close activities and driv

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As Engineer of MS H/MSB Lean Manufacturing, you will manage the implementation of Lean transformation methodologies and tools across High Bandwidth Memory (HBM), Component Assembly and Test, and SSD operations . You will collaborate closely with Site functional teams to identify , explore and implement lean methodologies/tool to uncover step-change area of improvement in throughput, labor productivity, yield and cycle time performance. Main Responsibilities: Facilitate continuous improvement event across different functional team (Kaizen, Value stream Mapping – VSM, Project, Workshop, etc ) <u

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. At Micron, we believe in encouraging a culture of innovation and excellence. The PDE Process Integration (PI) Senior Manager role offers an outstanding chance to lead a distributed team in defining, standardizing, and driving High Bandwidth Memory (HBM) New Product Introduction (NPI) success across several locations. This position blends strategic leadership, scaling of operations, and coordination across sites. It aims to ensure consistent PI readiness, faster yield ramp, and strong risk management from development through High Volume Manufacturing (HVM). Job Responsibilities Define and drive PI strategy, standards, and guidelines across HBM programs. Coordinate PI execution across multiple HBM NPI programs, ensuring delivery against network-level achievements and ramp targets. Ensure robust risk identification, early detection mechanisms, and mitigation strategies. Serve as the central PI leader collaborating with various engineering and manufacturing organizations. Champion the adoption of AI-enabled tools for yield analysis and risk prediction. Organizational Leadership & Talent Strategy Guide and grow a group of PI managers and senior engineers spanning several locations or departments.

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Description The MSH PDE Process Integration (PI) Manager leads a team of Process Integration engineers responsible for the successful execution of High Bandwidth Memory (HBM) New Product Introduction (NPI) from early development through High Volume Manufacturing (HVM) . This role combines people leadership, technical oversight, and cross‑functional execution , ensuring PI readiness, yield ramp, and risk mitigation across wafer fabrication, assembly, and test. The manager is accountable for delivering NPI commitments while developing a strong, scalable PI organization. Job Responsibilities People Leadership & Talent Development Lead, coach, and develop a team of MSH PDE PI engineers across multiple experience levels Set clear expectations, goals, and priorities aligned to NPI and business objectives Provide regular feedback, performance evaluations, and career development guidance Build organizational capability through hiring, onboarding, mentoring, and succession planning Foster a culture of accountability, collaboration, and technical excellence HBM NPI Execution & Delivery Own PI execution for HBM NPI programs, en

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Description As a Senior/Staff Product Quality and Reliability Assurance Engineer (PQRA), you will support reliability qualification and quality monitoring of High Bandwidth Memory products (HBM), help develop product reliability methodologies, and respond to product deviations as they pertain to quality and reliability. You will establish and implement requirements, specifications and metrics such as Defects per Million (DPM), Failure in Time (FIT), and Lifetime. In this role, you will work with multi-functional Engineering teams to ensure product reliability methods are established and followed, perform risk assessments, and provide support for manufacturing teams regarding reliability issues. In this dynamic role, you will have opportunities to gain new product knowledge on an ongoing basis! You will: Conduct New Product Qualifications Define High Bandwidth Memory (HBM) qualification requirements Comprehend failures and failure rate within the scope of the qualification Perform risk assessment at all decision points within the qualification cycle Review qualification data and sign off that qualification requirements have been met Issue internal product release notifications for Qualification <

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Description As a Senior/Staff Product Quality and Reliability Assurance Engineer (PQRA), you will support reliability qualification and quality monitoring of High Bandwidth Memory products (HBM), help develop product reliability methodologies, and respond to product deviations as they pertain to quality and reliability. You will establish and implement requirements, specifications and metrics such as Defects per Million (DPM), Failure in Time (FIT), and Lifetime. In this role, you will work with multi-functional Engineering teams to ensure product reliability methods are established and followed, perform risk assessments, and provide support for manufacturing teams regarding reliability issues. In this dynamic role, you will have opportunities to gain new product knowledge on an ongoing basis! You will: Conduct New Product Qualifications Define High Bandwidth Memory (HBM) qualification requirements Comprehend failures and failure rate within the scope of the qualification Perform risk assessment at all decision points within the qualification cycle Review qualification data and sign off that qualification requirements have been met Issue internal product release notifications for Qualification <

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. The TSE Technician – HBM Probe supports Test Solutions Engineering (TSE) activities for High Bandwidth Memory (HBM) products at wafer probe. The role executes operational, data, and system‑level tasks that enable efficient HBM probe evaluations, production releases, and yield/debug activities , working closely with TSE engineers across NPI and high‑volume manufacturing phases. This position is critical in supporting fast‑paced HBM development cycles where tight execution, data discipline, and cross‑functional coordination are essential. Key Responsibilities Support HBM probe activities by executing requests from TSE engineers, including: Evaluation and production lot assignment, tracking, and coordination Lot handling, status monitoring, and execution follow‑up Attribute tagging, traveler setup, and hold / release execution Support experiments and investigations related to: Yield improvement Test time optimization Test errors and probe‑related issues Perform data mining and generate reports with basic analysis to support: Engineering debug and root‑cause investigations NPI learning cycles and ramp readiness Production

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As a HIG PSE IE Senior Technician , you will support HBM IQP Reliability, Device Reliability, Package Reliability, Wafer Reliability, and product debug activities . The role includes reliability testing, failure analysis, laboratory operations, inventory and logistics management, audits, safety compliance, and continuous improvement initiatives. You will leverage Artificial Intelligence (AI) and AI-assisted tools to improve IQP reliability run rate management, enhance debug capabilities, support wafer-level reliability testing, and drive automation and digital transformation within the lab environment. Key Responsibilities Support Device Reliability, Package Reliability, and Wafer Reliability execution. Monitor and manage IQP reliability run rates, sample flow, and hardware readiness. Perform first-pass failure analysis and product debugging using probe stations and other debug tools. Utilize AI-assisted tools to improve debugging efficiency, root cause investigation, and operational planning. Support automation projects, data analysis, dashboard reporting, and process improvements. Manage procurement, inventory, logistics, and laboratory readiness activities. Support audits, document contr

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As a key talent within High Bandwidth Memory (HBM) Product & System Engineering Media Health team, you will work together with a high performing team driving both intrinsic and extrinsic reliability test development and execution for Micron’s latest HBM products, both on DRAM and Interface die and a stacked product. Your responsibility is to drive extrinsic DPM reduction (Time 0 and Field DPM) and lead the intrinsic reliability charter, along with optimized Manufacturing Test Flow to meet critical KPI’s Quality, Cost and Cycle Time. You will work within the team to characterize the products from reliability aspect, identify the reliability gaps, working on root cause and resolution of qual and RMA failures pertaining to defectivity and intrinsic reliability margin and drive fab process improvement driven by the qual failures. Additionally, your team will also be the key person in frontend process conversion, where you will work with Fab, TD, GQ teams to establish robust business process for process conversions to facilitate yield improvements, DPM and Cost Reduction. You will collaborate across functions within and outside of HBM to meet both strategic and tactical objectives while continually maximizing the effectiveness of the HIG HBM PE organization. The future of HBM are exciting and dynamics.

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. NVIDIA’s Silicon Co-Design Group is hiring a Chip Lead to serve as the technical lead for one of our most consequential silicon programs! This is not project management, and it is not a senior IC role. You are the person the program partners with on its hardest technical questions — when the right answer is not obvious, and when leadership needs a single technical perspective to align on direction. You are accountable for the technical integrity of the chip end-to-end. You guide co-design feature integration, help resolve the toughest multi-functional bugs, and serve as the project-specific custodian of the qualification playbook. The program runs cleaner because you are on it! What you’ll be doing: You will partner across design, validation, software, and manufacturing to keep the program’s technical narrative clear and on track. Day to day, you will: Serve as the single technical point of contact for multi-functional decisions, issues, and trade-offs. Co-lead program-level feature integration from chip to system, surfacing inter-function dependencies and guiding them to resolution. Help resolve the program’s hardest multi-functional bugs by translating ambiguous, multi-team symptoms into root-cause closure on areas such as HBM, power and thermal, high-speed I/O, and packaging. Steward the qualification playbook. When the playbook does not fit a situation, guide the mitigations and capture the lessons as reusable methodology for other SSG programs. Shape the program’s technical narrative by surfacing key risks, trade

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology and amazing people. Today, we're harnessing the boundless possibilities of AI to build the next era of computing. An era in which our GPU acts as the brain of computers, robots, and self-driving cars that can understand the world. Accomplishing unprecedented goals calls for imagination, inventiveness, and exceptional talent from around the world. As a NVIDIAN, you'll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. Join our team and discover how you can build a lasting impact on the world. NVIDIA's Silicon Co-Design Group (SCG) leads the full product development lifecycle, from early architecture definition through silicon bringup to product release. The ArchDev team is the hub for silicon and system-level feature development, driving tradeoff analysis, system integration, and POR alignment across the entire organization. This is where ideas become chips, and chips become products that define the state of the art — and we're building that future with some of the most motivated engineers in the industry. We're looking for a Senior Memory Systems Engineer to own HBM and LPDDR integration in sophisticated SoCs. This role covers the full stack, including silicon, package, embedded software, testing, and product development. The engineer will resolve the toughest system-level memory challenges throughout the process, building solutions that hold up at scale. What you'll be doing: HBM & LPDDR System Integration and Bringup: Drive HBM and LPDDR system integration, bringup, characterization, and debug for next-generation SoCs — taking memory subsystems through the full arc from first silicon to production-ready at scale. Full-Stack Memory Closure: <s

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As a Senior Engineer, MCT Operations Quality at Micron Technology, Inc., you will lead and collaborate closely with Global Assembly & Test (AT) sites, Global Quality, and various cross-functional stakeholders to drive on Manual Touchpoint Reduction. You will champion a Quality-First mindset by driving manufacturing solutions and end-to-end redesign initiatives to eliminate manual steps upfront that reduce operational error, prevent customer events and enhance product quality across Global AT network. Job Responsibilities: Lead global initiatives and collaborate with AT sites and Global Quality to identify and eliminate high-risk manual touchpoints across Assembly, Test/Post E, Module/SSD, HBM/PWF areas. Conduct onsite validation of the manual touchpoints at the source, identify quality risks, and propose improvements to eliminate the touchpoints. Collaborate with subject matter experts and drive the development and deployment of scalable solutions through physical automation/robotics, system automation, and Predictive Quality & Generative AI-enabled solutions. Collaborate with subject matter experts on end-to-end redesign initiatives to eliminate manual touchpoints upfront. Lead as the central team program governance to drive strategy, ali

What We’re Looking For: We’re looking for an XPU Architect to own the XPU compute engine architecture of the A-0 and A-1 systems. This will initially involve heavily leveraging existing 3rd party IP, but in a creative way to solve the bandwidth demand challenges and memory system interface challenges. Future generations of the compute XPU will be semi-custom and custom designs. Ideal Background: An ideal candidate will have: Previous experience architecting and owning a high performance, high TDP ASIC (eg AI chips, network switch chips, high performance CPUs or similar) Knowledge of both computer architecture but also silicon implementation, and understanding of the realistic constraints that silicon implementation places upon architectural options Deep understanding of AI workloads, especially low latency LLM inference Understanding of workload and system level bottlenecks, especially around inference, as it pertains to interconnect, memory capacity, bandwidth, latency, etc. Strongly Preferred: Hands-on experience with AI chip architecture and tapeouts End to end ownership of at least one AI ASIC project History of product delivery (regardless of ultimate commercial success of said product) Experience with HBM-based AI chip architecture Experience in proposing “weird” chip architectures (in any domain, not just AI!)

About the Team OpenAI’s Hardware organization is building the infrastructure foundation for frontier AI systems. The Supply Chain organization is responsible for enabling scalable, resilient, and efficient supply chains across custom silicon, systems, networking, memory, storage, and rack-scale infrastructure. The Supply Chain Program Manager (SCPM) drives end-to-end material readiness and supply chain execution across the hardware lifecycle, from early architecture and sourcing strategy through production ramp and sustaining operations. We are looking for experienced supply chain leaders who can operate across technical, commercial, and operational domains to ensure material readiness, supply continuity, and execution excellence for complex AI hardware programs. About the Role As a Supply Chain Program Manager, you will own material readiness and supply chain execution for critical hardware programs spanning custom silicon, systems, memory, storage, networking, and rack infrastructure. You will work cross-functionally with Engineering, Strategic Sourcing, Manufacturing Operations, Finance, Planning, Quality, and external suppliers to develop and execute scalable supply strategies that support aggressive product development and deployment timelines. This role requires deep understanding of hardware supply chains, material planning, NPI execution, supplier management, and operational scaling in constrained and rapidly evolving environments. Responsibilities Material Readiness & Supply Planning - Own end-to-end material readiness across NPI and production phases, including building the necessary framework and processes for enablement. Drive supply planning and execution for long lead-time and constrained commodities including ASICs, HBM, DDR, SSDs, networking, optics, power, thermal, and mechanicals. Build and manage material readiness plans aligned to proto/pre-EVT, EVT, DVT, PVT, and mass production schedules. Monitor supply health, lead times, inventory positio