High Performance Workstation Business Development Manager Amd Jobs

About the Role Together AI is building the AI Native Cloud, an end-to-end platform for the full generative AI lifecycle, combining the fastest LLM inference engine with state-of-the-art GPU cloud infrastructure. The Together Cloud team builds the [Together GPU Clusters](https://www.together.ai/gpu-clusters) flagship IaaS product that provides high-performance, AI-ready GPU clusters through a self-serve cloud console, along with the virtualized infrastructure layer powering Together's inference, RL, and fine-tuning products. As a Staff Software Engineer focusing on AI Compute in the Together Cloud org, you will set technical direction for and build major components of the next generation AI cloud platform – a highly available, global cloud infrastructure with cutting-edge virtualization of the latest ML hardware: GB300s/VRs, BlueField DPUs, InfiniBand and dual/quad-plane RoCEv2 fabrics. That virtualized computing platform powers our own SaaS products – inference, RL, and fine-tuning – and serves external cloud customers through self-serve offerings such as on-demand/reserved Kubernetes/Slurm clusters, across dozens of data centers and hundreds of thousands of GPUs. This is an architect-and-build role. Fully automated bootstrapping of GPU data centers, high-performance virtualization of GPU compute and DC networking without compromising isolation or portability, and fault-tolerant decentralized control planes — you'll set the architecture for these across our global and in-DC services, and be a key owner of the hardest parts, in the code as well as the design. Your designs will span the IaaS layer of a greenfield Vera Rubin data center up to the global management plane that schedules capacity across all of them. At this level the job is as much leverage as code: the standards you set and the engineers you grow decide how fast the rest of Together Cloud ships. Responsibilities Own the GPU and network virtualization stack: the hypervisor, kernel, and SDN work that keeps

Job Details: Job Description: The Role and Impact As a Physical Design Engineer, you will play a critical role in driving the development of cutting-edge technologies at Intel. You will work hands-on to deliver high-performance physical designs, ensuring the successful integration of advanced semiconductor technologies. Your work will directly impact Intel's product innovation, addressing complex challenges in power, performance, and area optimization to shape the future of computing architectures. From synthesis to sign-off, your contributions will enable Intel to meet ambitious design goals and deliver transformative solutions to the market. Business Group This role is part of Intel's Corporate Technology Office (CTO), a dynamic group dedicated to advancing the company's technological leadership and innovation. The group focuses on developing foundational technologies, architectures, and methodologies that drive Intel's product roadmap and enable breakthrough computing solutions. Collaborating with cross-disciplinary teams, the CTO plays a pivotal role in delivering impactful designs that support Intel's broader mission of creating world-changing technology. Key Responsibilities - Drive RTL-to-GDS design convergence using advanced synthesis and place-and-route tools targeting performance, power, and area (PPA) goals. - Deliver block-level physical design, including closure of backend flows, electrical requirements, and enhancing silicon yield. - Collaborate with CAD and physical design methodology teams to adopt industry-leading tools and optimizations for custom designs. - Execute physical implementation tasks such as floor planning, bus/pin placement, power/clock distribution, congestion analysis, timing closure, IR drop analysis, and physical verification. - Debug timing, EM/IR, LVS, and DRC violations, and driv

Job Details: Job Description: About the Role Join a team developing next-generation CPU cores that power client, server, IoT, and AI platforms. As a Senior Physical Design Engineer (CPU), you will play a key role in delivering high-performance, power-efficient silicon solutions. You will take ownership of blocks within the CPU core design, driving implementation from RTL to GDS and contributing to advanced physical design methodologies. What You’ll Do Key responsibilities will include but not limited to: Own physical design and implementation of CPU core blocks or subsystems Execute synthesis, floorplanning, place and route, and design closure Perform static timing analysis (STA), power analysis, and physical verification Drive convergence of timing, power, and area (PPA) metrics Debug and resolve complex design issues across multiple design stages Develop and optimize design flows and automation scripts Collaborate cross-functionally with RTL design, verification, clocking, and full-chip teams Contribute to improving design methodologies and best practices Provide guidance to junior engineers where applicable Behavioral traits that we are looking for: Strong problem-solving and analytical thinking Takes ownership and accountability for deliverables Collaborates effectively across multidisciplinary teams Communicates technical concepts clearly and concisely Prioritizes work effectively in a fast-paced environment Continuously learns and applies new tools and methodologies Why Join Us Work on cutting-edge CPU core designs that power client, server, IoT, and AI platforms used worldwide Be part of

GitLab is the intelligent orchestration platform for DevSecOps. GitLab enables organizations to increase developer productivity, improve operational efficiency, reduce security and compliance risk, and accelerate digital transformation. More than 50 million registered users and more than 50% of the Fortune 100* trust GitLab to ship better, more secure software faster. The same principles built into our products are reflected in how our team works: we embrace AI as a core productivity multiplier, with all team members expected to incorporate AI into their daily workflows to drive efficiency, innovation, and impact. GitLab is where careers accelerate, innovation flourishes, and every voice is valued. Our high-performance culture is driven by our values and continuous knowledge exchange, enabling our team members to reach their full potential while collaborating with industry leaders to solve complex problems. Co-create the future with us as we build technology that transforms how the world develops software. * Fortune 500® is a registered trademark of Fortune Media IP Limited, used under license. Claim based on GitLab data. Fortune 100 refers to the top 20% ranked companies in the 2025 Fortune 500 list, published in June 2025. Fortune and Fortune Media IP Limited are not affiliated with, and do not endorse products or services of GitLab. An overview of this role As a Senior Contracts Manager, Commercial (EMEA), you’ll help keep GitLab’s commercial contracting moving by managing a varied pipeline of customer agreements, from established contracting work to more involved and complex negotiations. You’ll work closely with sales and internal teams to keep deals on track while protecting GitLab’s interests. You’ll be part of the team that helps GitLab do business every day, bringing pace, precision, and good judgment to a broad range of commercial legal work. In this hands-on role, you’ll keep the day-to-day contracting work moving while also contributing to various s

GitLab is the intelligent orchestration platform for DevSecOps. GitLab enables organizations to increase developer productivity, improve operational efficiency, reduce security and compliance risk, and accelerate digital transformation. More than 50 million registered users and more than 50% of the Fortune 100* trust GitLab to ship better, more secure software faster. The same principles built into our products are reflected in how our team works: we embrace AI as a core productivity multiplier, with all team members expected to incorporate AI into their daily workflows to drive efficiency, innovation, and impact. GitLab is where careers accelerate, innovation flourishes, and every voice is valued. Our high-performance culture is driven by our values and continuous knowledge exchange, enabling our team members to reach their full potential while collaborating with industry leaders to solve complex problems. Co-create the future with us as we build technology that transforms how the world develops software. * Fortune 500® is a registered trademark of Fortune Media IP Limited, used under license. Claim based on GitLab data. Fortune 100 refers to the top 20% ranked companies in the 2025 Fortune 500 list, published in June 2025. Fortune and Fortune Media IP Limited are not affiliated with, and do not endorse products or services of GitLab. This is a future opportunity that may not be immediately available, but we're proactively building our pipeline of exceptional talent. At GitLab, we believe in connecting with outstanding professionals before we have an urgent need, allowing us to move quickly when the right moment arises. If you are excited about co-creating the future as we're building the most comprehensive AI-powered DevSecOps platform, we want to hear from you. Responsibilities TEXT Requirements TEXT Hiring Process TEXT Compensation To view the full job description and its compensation calculator, view our handbook. The compensation calculator can be f

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron’s DRAM Product Architecture Group partners across fabs, test, module, and system teams worldwide to deliver high-performance memory products. We work across geographies and functions to solve complex technical challenges, drive product innovation, and enable industry-leading DRAM solutions. Our team values collaboration, continuous learning, and making a measurable impact through engineering excellence. As a New College Graduate DRAM Yield & Quality Engineer, you will play a key role in monitoring and improving the health of Micron’s server DRAM products. Working with experienced engineers and cross-functional teams around the globe, you will analyze product and manufacturing data, investigate technical issues, and contribute to strategies that improve yield, quality, and performance throughout the product lifecycle. This is a highly visible role with direct impact on customer success and product reliability. Responsibilities Analyze silicon parametric, test, and manufacturing data to identify trends, resolve product issues, and support root cause investigations. Contribute to yield and quality improvement initiatives across new product introduction (NPI), qualification, ramp, and high-volume manufacturing. Collaborate with fab, test, module, quality, and operations teams to drive execution of product health objectives. Develop and maintain automation solutions to improve engineering efficiency, data analysis, and reporting. Apply AI, Agentic AI, and Generative AI tools to en

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, we are transforming how the world uses information to enrich life. The High Bandwidth Memory (HBM) Design team develops industry-leading memory solutions that enable advances in Artificial Intelligence, high-performance computing, graphics, and data-center applications. Our engineers collaborate across global teams to deliver innovative memory architectures and semiconductor technologies that power next-generation computing systems. As an HBM Design Engineer Intern, you will work alongside experienced memory engineers and gain hands-on experience in semiconductor design, simulation, verification, and analysis. This internship provides exposure to industry-standard design methodologies, EDA tools, and cross-functional collaboration throughout the product development lifecycle. You will also have opportunities to apply AI-Assisted and AI-Enabled workflows to improve engineering productivity, debug efficiency, and design quality. Responsibilities Assist with the design, simulation, analysis, and verification of HBM memory and logic circuits using industry-standard semiconductor design tools. Support RTL development, circuit implementation, timing analysis, power analysis, and functional validation activities. Develop scripts, automation solutions, and AI-Assisted workflows to improve design productivity, debug efficiency, and design-flow quality. Collaborate with Design, Verification, Physical Design, CAD, and Product Engineering teams on technical reviews, debug activities, and project deliv

Ignite your curiosity. Solve the unsolvable. At Leidos, we do more than write code—we decode the unknown. Our San Diego-based research and engineering team takes on some of the nation’s toughest defense challenges using advanced signal processing, ocean remote sensing, and high-performance computing. We’re seeking a Software Engineer / Computer Scientist who enjoys solving complex problems and pushing the limits of performance. In this role, you’ll work alongside a multidisciplinary team of scientists and engineers with expertise in hydrodynamics, physics, acoustics, and signal processing to build impactful software that turns massive, complex data sets into meaningful insight. If you are motivated by innovation, energized by collaboration, and excited to see your work support real-world missions, this could be the right opportunity for you. What You’ll Do Collaborate with scientists and engineers to design, develop, and optimize advanced algorithms for next-generation radar, optical, and infrared sensor systems. Build scalable, high-performance backend systems for scientific computing in distributed environments. Integrate, refactor, and improve scientific codebases to increase efficiency and scalability. Translate and optimize existing code for GPU/CUDA acceleration and parallel or distributed execution. Test, document, maintain, and enhance complex software in Linux/Unix environments. Contribute in a collaborative environment that values technical excellence, creativity, and continuous growth. Required Qualifications Bachelor’s degree in Computer Science, Applied Mathematics, Physics, or a related field with 4+ years of backend software development experience, or a Master’s degree with 2+ years of experience. Equivalent experience may be considered in place of a degree. U.S. citizenship and the ability to obtain a Top Secret clearance; active Top Secret clea

NVIDIA Architecture Modeling group is looking for Architects, Functional Modeling Engineers, and Simulation experts to join various architecture efforts across GPU/ SOC Architecture teams. A key part of NVIDIA's strength is to innovate in parallel computing fields, delivering the highest performance in the world for high-performance computing. We are constantly looking for ways to improve our SoC and Systems architecture and maintain our leadership. In this position, you will be working with other world-class architects on modeling, analysis and validation of chip & system architectures and features that advance the state of art in performance and efficiency. What you'll be doing: Modeling and analysis of SoC & Systems algorithms and features, across datacenter, automotive, and client products Build and deliver platforms for SOC's that enable left shift for the SW teams aligned with project milestones Work closely with the SOC architects and guide modeling teams to deliver high-quality functional models that involve SOC+GPU use cases Collaborate with our EDA partners to align on customer-facing technologies Develop tests, test plans, and testing infrastructure for new architectures/features and code coverage analysis and reporting Ensure alignment between the various modeling teams at NVIDIA, GPU modeling teams, and modeling teams overseas What we need to see: Master’s or PhD in Computer Science, Electrical Engineering, Computer Engineering, or a related relevant field (or equivalent experience) with 5+ years of relevant work experience. Strong programming ability: C++, C along with a good understanding of build systems (CMAKE, make) , toolchains (GCC, MSVC) and libraries (STL, BOOST) Computer Architecture background with experience in modelling wit

NVIDIA is seeking elite ASIC Verification Engineers to verify the design and implementation of the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will help to build the high-performance processor elements that implement programmable compute and graphics functionality. What you'll be doing: As a key member of our ASIC Verification team, you will verify the design and implementation of the industry's leading GPUs You will be responsible for verification of the ASIC design, architecture, golden models and micro-architecture using advanced verification methodologies such as UVM Understand the design and implementation of your unit, define the verification scope, develop the verification infrastructure and verify the correctness of the design Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks What we need to see: Bachelors Degree in EE, CS or CE or equivalent experience 2+ years of relevant experience Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies Background with design and verification tools (VCS or equivalent simulation tools, debug tools like Verdi, GDB) Experience crafting test bench environments for unit and system level verification Strong background in System Verilog or similar HVL Expertise with C/C++ programmin

What if the work you did every day could impact the lives of people you know? Or all of humanity? At Illumina, we are expanding access to genomic technology to realize health equity for billions of people around the world. Our efforts enable life-changing discoveries that are transforming human health through the early detection and diagnosis of diseases and new treatment options for patients. Working at Illumina means being part of something bigger than yourself. Every person, in every role, has the opportunity to make a difference. Surrounded by extraordinary people, inspiring leaders, and world changing projects, you will do more and become more than you ever thought possible. We are looking for a talented and motivated scientist to join the Assay Research and Development group. You will play an important role in developing new and novel sequencing library preparation assays that meet the high performance and robustness characteristics that our customers require. You will be responsible to design and execute experiments, collect data, perform analysis, draw conclusions and participate on product development teams. A background in molecular biology and biochemistry lab techniques is desired. Position Responsibilities: Designs and performs experiments of varying complexity and across a broad array of techniques, foresees issues and works to overcome obstacles to completing tasks or assignments, conceives of new ways to analyze the data and present it. Makes detailed technical observations and documents them in laboratory notebooks and confluence pages, etc. Plans, conducts, summarizes, reports consistent conclusions, and generates recommendations for follow up experiments and may suggest alternate strategies. <

Work Flexibility: Field-based What You’ll Do As an Orthopaedic Instruments Sales Representative, you will drive business growth by selling medical devices and surgical products within your assigned territory. You will leverage your strong communication, negotiation, and presentation skills to influence a wide range of stakeholders, while effectively managing complex sales cycles involving multiple decision-makers. Thriving in a fast-paced, high-performance environment, you take full ownership of your business—demonstrating strong organization, accountability, and time management as you work to consistently meet and exceed your sales goals. Develop and execute territory sales plans to achieve and exceed quota Build and maintain relationships with surgeons, operating room staff, SPD, supply chain, and hospital administrators Conduct product demonstrations, evaluations, and trials in clinical and operating room environments Support and lead product launches, conversions, and implementations Deliver in-services and training to clinical staff on proper product use Identify and advance new business opportunities and pipeline growth Analyze territory performance, track sales metrics, and communicate results to leadership Provide real-time problem solving in fast-paced surgical environments What you need Required: Bachelor’s degree OR 5&#43; years of outside sales, B2B sales, or territory management experience Preferred: 2&#43; years of experience in medical device sales, or healthcare sales, or B2B outside sales with quota responsibility, strongly preferred Proven track record of quota attainment, revenue growth, or territory expansion Experience selling into hospitals, physicians, healthcare systems, payroll, or B2B

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE Drive the hardware engineering lifecycle for Everpure’s Hyperscale Line of Business, shaping high-performance, energy-efficient storage architectures tailored directly to hyperscale partners . You will serve as the technical lead bridging customer requirements and internal engineering execution, ensuring custom hardware solutions meet exacting performance and total cost of ownership (TCO) benchmarks . Working closely with cross-functional teams in validation, diagnostics, manufacturing test, and operations, you will lead hardware qualification projects, solve critical escalations, and advance system robustness . This role gives you direct ownership over the hardware that powers next-generation, large-scale data infrastructure . WHAT YOU'LL DO Lead Hardware Qualification & System Hardening: Plan, execute, and automate comprehensive x86 hardware validation cycles—including electrical, signal integrity, and protocol testing—to guarantee system reliability for enterprise hyperscale deployments . Drive Cross-Functional Production Readiness: Partner with operations, manufacturing test, and software diagnostic teams to transition custom storage subsystems into full-scale production, establishing clear test coverage and automated validation workflows . Resolve High-Impact Technical Escalations: Perform root-cause analysis on complex hardware failures and field escalations, using advanced tools like high-speed o

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, we are transforming how the world uses information to enrich life. The High Bandwidth Memory (HBM) Design team develops industry-leading memory solutions that enable advances in Artificial Intelligence, high-performance computing, graphics, and data-center applications. Our engineers collaborate across global teams to deliver innovative memory architectures and semiconductor technologies that power next-generation computing systems. As an HBM Design Engineer Intern, you will work alongside experienced memory engineers and gain hands-on experience in semiconductor design, simulation, verification, and analysis. This internship provides exposure to industry-standard design methodologies, EDA tools, and cross-functional collaboration throughout the product development lifecycle. You will also have opportunities to apply AI-Assisted and AI-Enabled workflows to improve engineering productivity, debug efficiency, and design quality. Responsibilities Assist with the design, simulation, analysis, and verification of HBM memory and logic circuits using industry-standard semiconductor design tools. Support RTL development, circuit implementation, timing analysis, power analysis, and functional validation activities. Develop scripts, automation solutions, and AI-Assisted workflows to improve design productivity, debug efficiency, and design-flow quality. Collaborate with Design, Verification, Physical Design, CAD, and Product Engineering teams on technical reviews, debug activities, and project deliv

We are seeking an accomplished and highly strategic Group Manager, Ad Trafficking & Operations, with a minimum of 10 years of progressive experience in digital ad operations, including significant leadership and team management responsibilities. The ideal candidate will be a seasoned expert in ad serving technologies, particularly Google Campaign Manager 360 (CM360), and will possess a deep understanding of the digital advertising ecosystem. This role requires exceptional leadership skills to manage and mentor a team of Ad Trafficking Coordinators and Managers, drive operational efficiencies, ensure flawless campaign execution, and contribute to the strategic evolution of our ad operations capabilities. Responsibilities: Strategic Leadership & Department Oversight: Develop and implement strategic roadmaps for the Ad Trafficking and Operations department, aligning with overall company objectives and client needs. Lead and manage a group of Ad Trafficking Coordinators and Managers, fostering a high-performance culture, continuous improvement, and professional development. Oversee the entire ad trafficking workflow, from campaign setup to reporting, ensuring adherence to best practices, quality standards, and service level agreements (SLAs). Evaluate and recommend new ad tech solutions, tools, and processes to enhance operational efficiency, accuracy, and scalability. Operational Excellence & Process Optimization: Drive the standardization and optimization of ad trafficking processes, naming conventions, and quality assurance protocols across the group. Implement robust pre-launch and post-launch QA strategies to minimize errors and ensure impeccable campaign execution and data integrity. Champion the adoption of automation and innovative solutions to streamline workflows and reduce manual effort. Establish and monitor key performance indicators (KPIs) for the team, driving accountability and continuous perfo