Ie Layout Jobs

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Summary : As a Layout Engineer, you will apply strong industrial engineering concepts and logical problem‑solving to optimize production equipment layouts that maximize factory output. You will serve as the connection point between Manufacturing, Engineering, and Facilities by maintaining accurate layout documentation, supporting tool‑installation planning, and ensuring that all proposed layouts are feasible within the factory’s technical and schedule constraints. <s

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Lead front-end semiconductor fab design and process tool planning activities for new fab construction, expansion, and remodeling projects. Develop and maintain cleanroom layout strategies that optimize manufacturing capacity, operational efficiency, equipment accessibility, and future scalability. Evaluate and define tool siting plans, process area configurations, aisle strategies, and support space requirements to enable manufacturing objectives. Partner with Process Engineering teams to translate technology roadmaps and capacity requirements into executable facility and layout solutions. Collaborate with Facilities, Utilities, Construction, and AMHS teams to ensure successful integration of manufacturing equipment, infrastructure systems, and material handling networks. Drive footprint optimization, cleanroom utilization improvement, and layout scenario analysis through data-driv

IE Layout Engineer — MSB, Singapore. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all . ​ Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities: The Space Modeling Layout Manager needs to lead Layout planners to develop space and transfer optimization strategies for fab expansion, technology migration, and future intelligent fab development. Drive best-in-class space utilization, transfer efficiency, and cost-effective solutions through modeling, simulation, and data-driven decision making. AI proficiency or AI‑enabled ways of working where applicable to support Micron’s AI transformation and ensures roles are aligned to our future workforce needs. </p

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities and Tasks: • Establish and improve process condition and technology. • Upgrade process capability and reduce production cost. • Establish and modify process management projects. • Set up process parameters for a variety of semiconductor equipment. • Evaluation, promotion and planning of new equipment / materials. • Abnormal analysis and improvement. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities and Tasks Join us at Micron and be a part of a team that is transforming how the world uses information to enrich life for all. As an IE Layout Senior Engineer, you will play a crucial role in our mission with responsibilities that build our world-class environment: Drive the planning and build of Fab/Lab/Office layouts. Compose layouts for new expansion areas, ensuring flawless execution. Manage space expansion projects with proven efficiency and precision. Actively engage in Micron’s environmental sustainability projects to contribute to our ambitious goals. Define methodologies for layout planning optimization, aiming for outstanding results. Build intelligent systems that simplify layout planning and management processes. Tongluo site fab/non-fab layout planning Requirements To compete for this role, you must bring a combination of expertise and ambition: Bachelor’s degree in Engineeri

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities : ​ •Coordinate and collaborate with the Layout team, AMHS, HVM, FAC, OI, and other cross-functional stakeholders to develop strategic space solutions that reduce cross-fab transfer moves. •Strong data analysis skills to leverage data-driven methodologies in support of layout optimization and strategic space planning decisions. •Apply continuous improvement concepts to proactively identify gaps, propose improvement opportunities, and drive sustainable space and operational efficiency enhancements. •Optimize fab space and operational efficiency using Best Known Methods (BKM), ensuring competitive space costs and flexibility for future expansion. •Define standardized processes and methodologies for layout planning optimization. •Develop long-term space strategies to support the planning and construction of a brand-new intelligent fab. •Develop and implemen

IE Layout Senior engineer — Miaoli - Tongluo, Taiwan. Apply via Workday.

IE Layout - Office Layout Planning — 2 Locations. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. SUMMARY: At Micron, we focus on developing groundbreaking silicon-to-systems solutions. We handle technology development, advanced memory builds, product development, system development, and validation to create world-class memory solutions. In this position, you will collaborate with Micron’s global design, layout, and verification teams to develop high-quality physical layouts for cutting-edge DRAM products. You will gain hands-on experience in semiconductor layout building, physical verification, and industry-standard Electronic Compose Automation (EDA) tools. RESPONSABILITIES: Design and Verify All Levels of Analog and Digital Layout Use computer aided design software (i.e. Cadence, Calibre, etc.) Work with Design Engineers to floor plan and design layout Understand and follow verification protocols Apply custom and/or automated layout techniques to design pitch, array, and peripheral layout for digital and analog circuits. Collaborate with build engineering to understan

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Layout Designer, you will develop and prepare multi-dimensional layouts. You will provide detailed drawings of semiconductor devices from schematics and related geometry provided by design engineers, verify data integrity, and take the lead in major block developments. You’ll be encouraged to communicate optimally with other functional groups across global sites, e.g. TD, design, verification, and CAD. We’re seeking a self-starter who can learn rapidly and adapt quickly to changing priorities. What’s Encouraged Daily: Coordinate and prioritize logistics and resource allocations to meet scheduled deadlines and proactively develop methodologies for issue resolution Contribute to group management and technical innovation Time management skills and prioritizing tasks and deliver quality-controlled results. Contribute to projects in a globally distributed design/layout environment Contribute to the improvement of layout efficiency through the development of automation and new method

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Define physical design rules for current and future Non-Volatile Memory (NVM) technologies from conception to full production ramp. Interact with process integration team to keep all technology developments up to date, to ensure DR's are accurate. Interact with design teams to evaluate the feasibility of different layout and architecture options (i.e., design rule and process limitations). Interact across multi-disciplinary teams to understand product and test structure failures and their interaction with layout and mask generated data Support design rule checking (DRC) of both base and mask layers and interface with physical verification team. Define algorithms for generation of mask data from drawn base layer data. <

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities Design and maintain standard cells for new DRAM products on new technology Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies Characterization and modeling of Standard cells to provide timing/power model Quality Analysis of characterized liberty models in terms of performance, Power and Functionality Develop automation test bench/flow/tools to improve the work efficiency and help data analysis Co-work with international colleagues on developing new flows and tools for stdcells design Ability to identify stdcells design & char pain points suitable for AI-based automation and collaborate with cross‑functional teams to deploy scalable solutions. Requirements Good understanding of CMOS circuit design Good knowledge of CMOS device physics and layout Experience in total stdcells flow from DTCO development/ spec definition till lib release RTL/GDS f

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities Design and maintain standard cells for new DRAM products on new technology Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies Characterization and modeling of Standard cells to provide timing/power model Quality Analysis of characterized liberty models in terms of performance, Power and Functionality Develop automation test bench/flow/tools to improve the work efficiency and help data analysis Co-work with international colleagues on developing new flows and tools for stdcells design Ability to identify stdcells design & char pain points suitable for AI-based automation and collaborate with cross‑functional teams to deploy scalable solutions. Requirements Good understanding of CMOS circuit design Good knowledge of CMOS device physics and layout Experience in total stdcells flow from DTCO development/ spec definition till lib release RTL/GDS f

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities Design and maintain standard cells for new DRAM products on new technology Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies Characterization and modeling of Standard cells to provide timing/power model Quality Analysis of characterized liberty models in terms of performance, Power and Functionality Develop automation test bench/flow/tools to improve the work efficiency and help data analysis Co-work with international colleagues on developing new flows and tools for stdcells design Ability to identify stdcells design & char pain points suitable for AI-based automation and collaborate with cross‑functional teams to deploy scalable solutions. Requirements Good understanding of CMOS circuit design Good knowledge of CMOS device physics and layout Experience in total stdcells flow from DTCO development/ spec definition till lib release RTL/GDS f