Layout Designer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an HBM Memory Design Engineer in Micron’s HBM Architecture Team, you will design, simulate, analyze, and floorplan digital and analog DRAM circuits used in advanced HBM technology. You will evaluate block-level and full-chip functionality, perform architectural pathfinding, and contribute to the development of next‑generation high‑bandwidth DRAM solutions. This role works across diverse engineering teams to deliver functionally accurate, low‑power, and high‑performance HBM products by bringing to bear 3D stacking and TSV-based integration. Responsibilities • Design, simulate, and optimize digital and analog DRAM circuits including data path, ECC, command/control, and high‑speed timing structures • Evaluate full‑chip and block‑level functionality and propose solutions to achieve correct circuit and system behavior • Perform timing, area, power, and complexity analysis for high‑speed DRAM and mixed‑signal circuits • Conduct pathfinding studies and feasibility analyses for future HBM architectures • Contribute to the development, layout, and optimization of memory, logic, and analog circuits • Analyze circuit behavior under varying PVT and parasitic conditions to ensure robust operation • Collaborate with multi-functional teams across build, verification, product engineering, process, and packaging • Support design reviews, documentation, and continuous improvement of design methodologies Minimum Qualifications • BSEE with 7+ years, or MSEE with 5+ years of releva

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Product Yield Enhancement (PYE) Electrical Failure Analysis (EFA) Engineer, you will work with a team dedicated to improving yields of next-generation memory products across all stages of the manufacturing lifecycle. Through failure analysis of test, internal qualification, and RMA failures, you will identify and help eliminate yield-limiting defects — driving enhanced product reliability, rapid production ramp, and early time to market. Your day-to-day work will center on fault isolation using a combination of electrical and physical characterization techniques paired with data analysis to pinpoint physical defects introduced during process fabrication or package assembly. You will also be responsible for presenting and coordinating failure analysis findings with Management, Product, Process, Assembly, and Global Quality teams to ensure corrective actions are implemented and yields continue to improve. Responsibilities Perform Electrical Failure Analysis and Fault Isolation using emission microscopy, laser techniques, EOTPR, and PFA/de-processing methods Characterize and model backend test, internal qualification, and RMA fail signatures using layout, schematic, and data analysis tools Apply in-depth knowledge of CMOS fabrication processes and package assembly flows to identify process- and assembly-related defects, root causes, and downstream effects Evaluate reliability concerns and delayed breakdown failure mechanisms across test insertions Perform

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. About the Role We are looking for a passionate and innovative ATE Test Engineer to design and deliver cutting-edge test solutions for HBM-DRAM devices using modern advanced ATE platforms. In this role, you will lead the development and implementation of test plans, ATE test programs, silicon validation, and test methodologies, while driving multi-site hardware design and development, product characterization, and high-volume production support. Success in this position requires a forward-thinking mindset and the ability to apply the right technologies to meet evolving challenges. Key Responsibilities Develop and implement robust test strategies, plans, and ATE programs for HBM-DRAM devices. Drive silicon validation, characterization, and yield improvement initiatives. Design and debug test hardware, including schematic capture and PCB layout. Collaborate cross-functionally to ensure seamless integration of test solutions into production. Support high-volume manufacturing and troubleshoot complex test issues. Qualifications & Skills Education: Bachelor’s or Master’s degree in Electrical, Electronics or Computer Engineering. Experience: A

Instawork is on a mission to create meaningful economic opportunities for skilled hourly professionals in communities around the globe. Our AI-powered labor marketplace helps local businesses scale, and enables global technology companies to push the frontiers of robotics and AI. Backed by world-class investors like Benchmark, Spark Capital, Craft Ventures, Greylock, Y Combinator, and others, we’re looking for exceptional talent to reimagine the way the world works. About the Role We are seeking a proactive, detail-oriented, and high-energy Office Coordinator to oversee the day-to-day functions, facilities, and workplace culture of our Bangalore offices . Reporting directly to the Office Manager, you will be the heartbeat of our local workspace—ensuring a clean, seamless, and highly productive environment for our team. If you are a collaborative problem-solver who thrives on operational efficiency, vendor management, and creating an amazing workplace experience, we want to hear from you! Working days - 6 days/week Key Responsibilities 🏢 Facilities & Office Operations Daily Functions: Own the upkeep of common areas, workspaces, and conference rooms, ensuring all furniture and audio/video (AV) equipment are fully operational. Vendor & Supply Management: Proactively manage relationships with external service providers (property management, furniture vendors, snack/catering programs, custodial services, etc.) and keep office supplies fully stocked. Ticketing & Support: Provide timely, high-quality responses to internal service requests assigned to the facilities queue. Space Planning: Assist the Office Manager with employee seating arrangements, desk allocations, and office layout planning. Cross-Functional Support: Coordinate with onsite facility staff and address ad hoc projects directed by the IT, People (HR), and Finance teams as aligned with the Office Manager. 🎉 Culture & Employee Engagement Cultural Stewardship: Act as a culture champion by supp

About Us SharkNinja is a global product design and technology company, with a diversified portfolio of 5-star rated lifestyle solutions that positively impact people’s lives in homes around the world. Powered by two trusted, global brands, Shark and Ninja , the company has a proven track record of bringing disruptive innovation to market and developing one consumer product after another has allowed SharkNinja to enter multiple product categories, driving significant growth and market share gains. Headquartered in Needham, Massachusetts with more than 4,100 associates, the company’s products are sold at key retailers, online and offline, and through distributors around the world. AI at SharkNinja At SharkNinja, we’re building an AI-native culture. We’re not waiting for the future; we’re creating it. Our people are expected to experiment boldly, adopt new tools, and continuously raise what’s possible to create meaningful impact for our consumers. If you believe the best way to do your job hasn’t been invented yet, you’ll fit right in. Director, Electrical Engineering – Corded & Cordless Products Needham, MA Lead the Electrical Engineering Behind Products Used in Millions of Homes SharkNinja's corded and cordless product portfolio spans some of the most technically demanding categories in consumer electronics — and the electrical engineering that powers them has to be exceptional. We're looking for a Director of Electrical Engineering to lead that work: a hands-on technical leader who can drive complex programs from early concept through high-volume production, and build a team that sets the standard for how we design and deliver hardware. This is a role for someone who leads from the front. You'll be as comfortable reviewing a PCB layout or debugging a motor control circuit as you are presenting to senior leadership or partnering with contract manufacturers overseas. You set the technical bar, and your team

P-1093 At Databricks, we are passionate about enabling data teams to solve the world’s toughest problems — from making the next mode of transportation a reality to accelerating the development of medical breakthroughs. We do this by building and running the world’s best data and AI infrastructure platform so our customers can use deep data insights to improve their business. Founded by engineers — and customer obsessed — we leap at every opportunity to tackle technical challenges, from designing next-gen UI/UX for interfacing with data to scaling our services and infrastructure across millions of virtual machines. And we're only getting started. The ManagedTables team at Databricks is responsible for the DataIntelligence initiatives that underpin the Unity Catalog ManagedTables offering. This encompasses products such as Predictive Optimization, Liquid Clustering, and control plane services facilitating Unity Catalog and Iceberg Rest Catalog API-based access to ManagedTables. The team is accountable for optimizing exabytes of data and saving millions of dollars annually for our customers through the Data Intelligence offerings. As part of this team, you will be working on realizing enterprise grade autonomous analytical datasystems - that ensure the best performance out-of-the-box. You will design and implement these next gen systems that leapfrog state-of-the-art: Storage lifecycle and additional background optimizations for a knob-free experience via Predictive Optimization Efficient storage structures and innovations to power storage layout solutions for the ML world Influence the Data format and Catalog interface unification efforts and enable strong ecosystem interoperability for ManagedTables The Impact you will have: Solve real business needs at large scale by applying your software engineering experience and by driving strong collaboration with Product partners Deliver a highly scalable, available, and inter-operable architecture for Managed Tables. Lo

About Us At LangChain, our mission is to make intelligent agents ubiquitous. We build the foundation for agent engineering in the real world, helping developers move from prototypes to production-ready AI agents that teams can rely on. We began as widely adopted open-source tools and have grown to also offer a platform for building, evaluating, deploying, and operating agents at scale. With $125M raised at Series B from IVP, Sequoia, Benchmark, CapitalG, and Sapphire Ventures, we’re at a stage where we’re continuing to develop new products, growth is accelerating, and all team members have meaningful impact on what we build and how we work together. LangChain is a place where your contributions can shape how this technology shows up in the real world. Today, our platform includes LangSmith (Observability, Evaluation, Deployment, Fleet, and Sandboxes), our open source frameworks (LangChain, LangGraph, and Deep Agents), and the newly launched LangSmith Engine for autonomous agent improvement. We have 100M+ monthly open source downloads, 6,000+ active LangSmith customers, and 5 of the Fortune 10 use LangSmith in production (+ 35% of the Fortune 500 overall), including teams at Klarna, Clay, Coinbase, Workday, Lyft, Cloudflare, Harvey, Rippling, Vanta, LinkedIn, Monday.com, Nvidia, and Bridgewater. About the team SmithDB is LangChain's internal database team. We're building a storage and query layer purpose-built for AI observability and evaluation. Within six months we went from idea to a production system that offers industry leading performance and scalability for agent observability data. We're a small, fast team of systems engineers tackling genuinely hard problems: storage layout, query execution, compaction, and scaling toward trillions of agent traces. We develop in Rust, run on Kubernetes, and integrate tightly with S3/GCS/Azure Blob. There are no legacy constraints; this is a greenfield system with real production load and ambitious engineering goals. About th

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of Micron’s HBM design organization, building the test architectures that enable the most advanced memory products in the world. Our team works at the intersection of design, manufacturing, and silicon learning to make 3D‑stacked memory reliable at scale. We thrive on deep technical challenges and close collaboration across disciplines! As an HBM Design Architect, you will define how next‑generation HBM products are tested from wafer to system. This role is critical to ensuring quality, yield, and performance across complex multi‑die architectures. You’ll influence product success early, work hands-on with silicon, and partner closely with design, test, and manufacturing teams. Responsibilities: Define and implement end-to-end DFT architectures for HBM base die and DRAM die Develop DFT strategies for stacked-die, cube-level, and system-level test flows Architect test access mechanisms supporting wafer probe through final test Enable silicon observability for yield learning, debug, and failure analysis Collaborate across design, verification, layout, test, and manufacturing teams Minimum Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field Strong knowledge of scan, MBIST, JTAG, and boundary scan concepts Experience with wafer probe and fin

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Role Summary The DMTS is a recognized expert inside and outside Micron, shaping the technical vision for cell film processes with influence across top-level organizational boundaries, leading programs spanning the engineering group, driving breakthroughs, influencing industry/cross-disciplinary teams, and mentoring senior technical leaders to guide critical roadmap decisions. Owns and updates the cell film process technology roadmap; drives external collaborations and benchmarking; prepares high-impact technical deliverables (presentations/white papers/patent filings); guides investment and prioritization decisions. Main Responsibilities Serve as the CMP technical authority for NAND technology development, defining long‑term technology and equipment strategies Architect and drive next‑generation CMP process innovation, including FOAK developments, recipe architecture, and integration alignment Lead resolution of the most complex yield, defectivity, and integration challenges through deep CMP process, materials, and layout expertise Define and execute CMP hardware and supplier roadmaps, translating industry benchmarking and external insights into internal advantage Provide forward‑looking technical leadership, identifying sc

1418 Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin, which will play a central role in Graphcore's work building the future of AI computing. The Electrical Engineer will play a pivotal role in designing innovative hardware systems for AI/ML applications. We are seeking a motivated Electrical Engineer with 2–4 years of experience in schematic capture, PCB design, and server hardware development. This role includes close collaboration with multiple partners to drive designs from concept through mass production. The ideal candidate is comfortable working across organizational boundaries, ensuring design quality, manufacturability, and on-time delivery in a fast-paced environment. Responsibilities: Develop and maintain electrical schematics for various printed circuit assemblies Design and layout multilayer PCBs Work closely with partners to review designs, provide technical guidance, and ensure alignment with system requirements Drive design for manufacturability (DFM), design for assembly (DFA), and design for testability (DFT) Support server subsystem integration Participate in design reviews Support prototype builds, board bring-up, debugging, and validation Track and resolve design issues, including root cause analysis and corrective actions Ensure proper documentation, revision control, and engineering change management (ECO/ECN processes) Requirements: Bachelor’s degree in electrical engineering 2–4 years of experience in schematic capture and PCB design

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities Design and maintain standard cells for new DRAM products on new technology Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies Characterization and modeling of Standard cells to provide timing/power model Quality Analysis of characterized liberty models in terms of performance, Power and Functionality Develop automation test bench/flow/tools to improve the work efficiency and help data analysis Co-work with international colleagues on developing new flows and tools for stdcells design Ability to identify stdcells design & char pain points suitable for AI-based automation and collaborate with cross‑functional teams to deploy scalable solutions. Requirements Good understanding of CMOS circuit design Good knowledge of CMOS device physics and layout Experience in total stdcells flow from DTCO development/ spec definition till lib release RTL/GDS flow setup, block level timing analysis, ICC2 experience. Preferred Synopsys EDA flow Finefet & planner experience required. Experience in any characterization tools (Siliconsmart/Liberate)and Cadence Virtuoso preferred. Experience in Primetime, Solido Analytics Familiar with analog/digital simulation tools, i.e. HSPICE, HSIM, VerilogHDL, FINESIM, Simvision Experience in Standard Cell design, layout and verification Experience in Skill, TCL, Per

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job / Role Summary The Staff Engineer leads module ‑ level photolithography process development for advanced NAND technology nodes. This role owns process robustness, manufacturability, and readiness for technology transfer. Success requires strong technical depth, execution leadership, and the ability to translate device requirements into reliable, scalable process solutions. Main Responsibilities Lead development, optimization, and troubleshooting of photolithography processes to meet yield, quality, and performance requirements. Translate device and integration requirements into robust process flows, specifications, and control strategies. Perform and own material evaluations, OPC/layout development, process window analysis, and overlay optimization. Design and implement advanced process control methodologies using SPC, DOE,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities Design and maintain standard cells for new DRAM products on new technology Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies Characterization and modeling of Standard cells to provide timing/power model Quality Analysis of characterized liberty models in terms of performance, Power and Functionality Develop automation test bench/flow/tools to improve the work efficiency and help data analysis Co-work with international colleagues on developing new flows and tools for stdcells design Ability to identify stdcells design & char pain points suitable for AI-based automation and collaborate with cross‑functional teams to deploy scalable solutions. Requirements Good understanding of CMOS circuit design Good knowledge of CMOS device physics and layout Experience in total stdcells flow from DTCO development/ spec definition till lib release RTL/GDS flow setup, block level timing analysis, ICC2 experience. Preferred Synopsys EDA flow Finefet & planner experience required. Experience in any characterization tools (Siliconsmart/Liberate)and Cadence Virtuoso preferred. Experience in Primetime, Solido Analytics Familiar with analog/digital simulation tools, i.e. HSPICE, HSIM, VerilogHDL, FINESIM, Simvision Experience in Standard Cell design, layout and verification Experience in Skill, TCL, Per

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Key Responsibilities: Lead development and optimization of photolithography processes to achieve yield, quality, and performance targets for advanced technology nodes. Define and convert future device requirements into reliable process specifications and equipment roadmaps. Drive early adoption of innovative process and equipment solutions to improve margin and manufacturability. Identify and integrate exciting technologies into production flows. Collaborate with global R&D teams and manufacturing sites to ensure seamless technology transfer. Partner with suppliers to accelerate breakthrough solutions and maintain strategic vendor relationships. Implement advanced process control methodologies using statistical tools, DOE, and simulation software. Conduct material evaluations, reticle/layout/OPC development, process window analysis, and overlay optimization. Develop intellectual property via patents and publications; deliver technical mentorship and guide technology strategy. Required Qualifications: Ph.D. in Electrical Engineering, Materials Science, Phys

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As a Principal/MTS Photolithography Process Development Engineer in Micron's R&D Technology Development group, you will lead advanced photolithography process development for next-generation memory devices, driving innovation in process integration and technology transfer across Micron’s global manufacturing network. Key Responsibilities: Lead development and optimization of photolithography processes to achieve yield, quality, and performance targets for advanced technology nodes. Define and translate future device requirements into robust process specifications and equipment roadmaps. Drive early adoption of innovative process and equipment solutions to enhance margin and manufacturability. Identify and integrate disruptive technologies into production flows. Collaborate with global R&D teams and manufacturing sites to ensure seamless technology transfer. Partner with suppliers to accelerate breakthrough solutions and maintain strategic vendor relationships. Implement advanced process control methodologies using statistical tools, DOE, and simulation software. Conduct material evaluations, reticle/layout/OPC development, process window analysis, and overlay optimization. Generate intellectual pro