Manufacturing Alignment Engineer Jobs

Use Your Power for Purpose Every day, Pfizer’s unwavering commitment to quality ensures the delivery of safe and effective products to patients. Our science and risk-based compliant quality culture is both flexible and innovative, always putting the patient first. Whether you are involved in development, maintenance, compliance, or research analysis, your contribution directly impacts patients. What You Will Achieve In this role: The incumbent is a member of the Quality Environmental Control (EC) Laboratory team. Under the supervision of the Environmental Monitoring (EM) Section Manager, and designated EM Shift Team Leader(s), the incumbent will be responsible for the collection, analysis, and inspection of manufacturing environmental conditions and materials according to Standard Operating Procedures (SOPs). Samples can include both physical and microbiological, air, surface, and water system products, as well as commodity items. In addition, the incumbent shall be responsible for both physical and microbiological, collection and analysis of pharmaceutical waters, raw materials, active pharmaceutical ingredients (APIs), and finished products according to Standard Operating Procedures (SOPs). Assays to be performed will be qualitative, quantitative, and investigational in nature and are performed in compliance with USP, FDA, other regulatory body requirements, Pfizer SOPs, and approved license requirements. Aseptic gowning practices will also be adhered to for the performance of activities as required. Results are compared with specifications, documented as per data integrity regulations, and incumbent is responsible for providing communication of all process and specification deviations. Incumbent has working knowledge of EM, microorganism handling, aseptic technique, and quality concepts as to perform routine assignments with minimal supervision. Additional responsibility may include performing data trending

Job Title Production Planner Job Description Production Planner Your Role: Job Responsibilities: • Ensures on-time delivery of customer orders by managing the quality of planning-related master data in close cooperation with Enterprise Information Management (EIM). • Generates a feasible/final Master Production Schedule (MPS) from the Initial/semi-final MPS provided by the Supply Planning function. • Develops a feasible Detailed Production Schedule (DPS) and Material Requirements Plan (MRP) from the MPS while minimizing changeover times in collaboration with Production/Operations Management. • Works diligently to optimize the utilization of both workforce and equipment, strategizing to enhance efficiency and productivity across production operations. • Coordinates planning-related master data in concert with Enterprise Information Management (EIM), ensuring data integrity and consistency to facilitate effective decision-making. • Releases meticulously crafted production schedules to the shop floor, ensuring that operational activities align seamlessly with organizational objectives and priorities. • Facilitates regular and structured planning handshake meetings with Production/Operations Management, fostering open communication channels to address challenges, align priorities, and drive operational excellence. • Engages in troubleshooting production orders and materials, promptly identifying and resolving issues to maintain operational continuity and uphold delivery commitments. You Are a Great Fit If: • Bachelor’s degree in computer science, Software Engineering, Electronics, Information Technology, or a related engineering discipline. • Minimum 2 years till 5 years of experience in production plant or manufacturing site or equivalent. Exte

Work Flexibility: Hybrid I am delighted to share that we are now accepting applications for our Stryker Advanced Operations (AO) Global Engineering Development Programme (AOGEDP) – to begin in September 2027. If you are an upcoming or recent graduate in a Level 8 or above Engineering, Software or Digital discipline-based Degree, then this is the opportunity for you! Advanced Operations (AO) is Stryker’s function that specialises in new product introductions across all of our divisions. The “ AO Global Engineering Development Programme ” is a 2 0 - month structured programme that provides participants the opportunity to be part of a global team, with exposure to cutting edge technology varying from traditional manufacturing processes to a dditive manufacturing and Robotics, as well as interactions with market leading Product Development , Quality Assurance and Operations teams from across the 9 Stryker divisions. The programme focuses on developing the skillset s , mindset and toolkit of each participant to enable them for success within Advanced Operations to

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. System Integration sits at the intersection of all of them. It is the layer where every architecture, design, software, and manufacturing decision meets reality. When something breaks late in a program, it usually breaks here first. We are hiring a Senior Manager to lead this team in the US and partner closely with teams globally. Your work will sit on the critical path of every NVIDIA silicon program, and the bar you set for system integration is the bar we ship to! The two hardest, highest-leverage problems in this seat: Find critical silicon issues earlier — often before software is production-ready. Left-shifting post-silicon coverage is the highest-value thing System Integration can do. Standing up wide-area testing as a repeatable capability is a core part of the role. Keep programs on milestone when upstream dependencies slip. Validation plans collide with reality every program! The team needs new strategies, not just contingency plans, to keep moving when software, firmware, or methodology slip. You will design and run those strategies. What you’ll be doing: Plan and execute post-silicon feature integration, PVT validation, and wide-area testing across NVIDIA’s GPU, SoC, and CPU programs. Build wide-area and in-system test as a repeatable capability that shifts post-silicon coverage left, so issues surface before we are production-ready. Lead resolution of the most complex system-level issues, RMAs, and HW/SW interaction problems with creative workarounds and focused lab experimentation. Deve

NVIDIA’s Silicon Co-Design Group is the team that gets every GPU, SoC, and CPU silicon program from first power-on to high-volume production. We are hiring a Senior Manager to lead our Test, Manufacturability, Reliability & Quality (TMRQ) organization. This is not a coordination role . Your work decides if a product can be built at scale and trusted in the field. These include production test development (SLT, BLT), control run flow, system reliability stress (HTOL), platform- and board-level manufacturing issue closure, and field diagnostic test development. You lead a team of individual contributors and a first-line manager at the layer where silicon, platform, and software collide with manufacturing reality. Decisions you make show up in yield curves, production ramp , and customer escapes. You are the leader the program turns to when a build is stuck, a control run is fallout-heavy, or a field return points back at silicon . The exceptional hire also uses AI deliberately — with demonstrated workflow impact and the judgment to know where it compresses real work and where it introduces risk. What you will be doing: Keep programs moving. Own the technical execution and velocity of SLT, BLT, Board/Chip/Rack CR, and system reliability stress (HTOL) across every GPU, SoC, and CPU silicon program. Close the hardest multi-functional failures. Resolve Vmin and binning escapes, performance shortfalls, and power anomalies by driving root-cause across design, methodology, DFT, ATE, package, software/firmware, and manufacturing — and own the WARs and productized fixes through to confirmation. Give leadership the clarity to act. Convert raw integration signals — CR fallout, BLT/SLT yield, SHTOL/CHTOL data, RMA trends, customer escalations — into decision-ready options that enable executive leadership to act with confidence on POR, QS/PS gates, a

Distinguished Technologist - Principal Architect, Platform Security and Firmware Systems Description - HP is seeking a senior technical leader to serve as a lead architect for hardware rooted Platform Root of Trust for HP's commercial PC platform. In this role, you will be responsible for envisioning, defining, and driving the architecture of hardware, firmware, software, and cloud-integrated security capabilities that protect HP commercial PCs from current and emerging threats. You will also work across the hardware and security architecture teams, collaborate with HP's Security Research Labs, Firmware (BIOS) team, our security business that creates and deploys industry leading enterprise security and manageability solutions, product management, manufacturing, supply chain, customer enablement, and field organizations to create cohesive system solutions that deliver unique customer value. This position requires deep expertise in embedded systems, platform firmware, hardware, security, device manageability, and PC system architecture. The role also requires the ability to translate complex technical capabilities into customer-relevant value propositions and to influence internal and external stakeholders without relying solely on formal authority. Responsibilities Serve as principal architect for HP Endpoint Security Controller roadmap, associated hardware and firmware based capabilities, cryptographic identity, attestation, secure communication, event logging, and future controller generations. Define and evolve HP Sure Start architecture and related firmware resilience capabilities, including hardware-enforced firmware authenticity, recovery, update, and protection mechanisms. Drive secure BIOS and firmware configuration management strategies, including HP Sure Admin ecosystem capabilities, key management, zero-touch provision

Job Details: Job Description: Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans Intel's research divisions and partnerships with leading academic institutions worldwide. We are seeking an exceptional Quantum Packaging Modeling Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for thermal modeling and simulation of various packaging solutions from silicon redistribution layers to IC substrates within a multidisciplinary team. You'll play a crucial role in advancing Intel's silicon quantum dot technology while contributing to the development of scalable quantum systems that will revolutionize computing. Key Responsibilities - Thermal modeling and simulation of packaging hardware to understand how heat flows from silicon test chips through various heat spreader hardware - Manage the overall integration of the packaging hardware and enable co-design between relevant stakeholders - Work closely with mechanical designers to define heat spreaders for optimal performance - Deliver and disseminate design milestones to stakeholders - Communicate designs in presentations and relevant documentation - Stay current with the latest developments in packaging technology and design techniques by attending conferences and rea

Job Details: Job Description: Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans Intel's research divisions and partnerships with leading academic institutions worldwide. We are seeking an exceptional Quantum IC Substrate Package Layout Design Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for design of large form factor IC substrates within a multidisciplinary team. You'll play a crucial role in advancing Intel's silicon quantum dot technology while contributing to the development of scalable quantum systems that will revolutionize computing. Key Responsibilities - Design of IC substrates using Siemens Xpedition IC package design software - Work closely with stakeholders to meet design requirements - e.g., receive feedback from silicon testchip, signal integrity (SI), power integrity (PI), thermal simulation, and system integration engineers - Deliver and disseminate design milestones to stakeholders - Design validation and verification; including DRC and LVS - Advanced packaging design integration (2.5D and 3D) with IC substrate - Tapeout of designs with substrate suppliers in collaboration with Intel substrate teams - Communicate designs in presentations and relevant documentation - Stay curre

JLL empowers you to shape a brighter way . Our people at JLL are shaping the future of real estate for a better world by combining world class services, advisory and technology for our clients. We are committed to hiring the best, most talented people and empowering them to thrive, grow meaningful careers and to find a place where they belong. Whether you’ve got deep experience in commercial real estate, skilled trades or technology, or you’re looking to apply your relevant experience to a new industry, join our team as we help shape a brighter way forward. GMP Cleaner - JLL What this job involves: This position requires strict adherence to current Good Manufacturing Practices (cGMPs), established cleaning policies and procedures, to maintain compliance with quality standards and FDA regulations. The incumbent plays a critical role in assuring sanitary conditions of the controlled areas are maintained, to allow for the manufacturing of biopharmaceuticals. Standard Operating Procedures (SOPs) must be followed and strictly enforced to ensure acceptable environmental monitoring results of the cleaned GMP environment are maintained. Appropriate room and equipment sanitization records are neat and accurate, and that professional behavior is always displayed within the controlled areas. What your day-to-day will look like: Perform sanitization and cleaning per governing SOPs in GMP spaces Sanitization activities will be performed with ceiling mops, wall mops, floor mops, and wipers Responsible for verifying that the proper sanitization disinfectant rotation is followed, and that the proper sanitization disinfectant is used for each cleaning assignment Strictly follow Standard Operating Procedures Responsible for completing required GMP documentation to ensure records are properly and accurately maintained Responsib

Job Details: Job Description: Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans Intel's research divisions and partnerships with leading academic institutions worldwide. We are seeking an exceptional Quantum Interposer Design Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for physical design and integration of advanced packaging interposers within a multidisciplinary team. You'll play a crucial role in advancing Intel's silicon quantum dot technology while contributing to the development of scalable quantum systems that will revolutionize computing. Key Responsibilities - Physical design and integration of interposers used within advanced packaging for quantum computing - Work closely with stakeholders to meet design requirements - e.g., receive feedback from silicon testchip, signal integrity (SI), power integrity (PI), thermal simulation, and system integration engineers - Design validation and verification; including DRC and LVS - Deliver and disseminate design milestones to stakeholders - Communicate designs in presentations and relevant documentation - Stay current with the latest developments in packaging technology and design techniques by attending conferences and reading papers As

Job Details: Job Description: Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans Intel's research divisions and partnerships with leading academic institutions worldwide. We are seeking an exceptional Quantum Packaging Signal/Power Integrity (SI/PI) Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for modeling and simulation of various packaging solutions from silicon redistribution layers to IC substrates within a multidisciplinary team. You'll play a crucial role in advancing Intel's silicon quantum dot technology while contributing to the development of scalable quantum systems that will revolutionize computing. Key Responsibilities - Modeling and simulation of packaging hardware including redistribution layers (e.g., interposers, RDLs), IC substrates, and silicon testchip routing - Work closely with stakeholders to meet design requirements - requirements come from both theory and hardware teams. In some pathfinding projects, you will be asked to participate in creating requirements and novel packaging hardware. - System-level modelling and simulation; end-to-end simulations to ensure designs meet system-level requirements - Deliver and disseminate design milestones to stakeholders - Communicate designs in pr

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job / Role Summary The Staff Engineer owns defined Realtime Defect Analysis (RDA) scope within NAND Technology Development, developing and sustaining advanced defect detection and inspection strategies that accelerate learning, improve yield, and support technology transfer to manufacturing. This role leads defect analysis, inspection recipe and sampling optimization, excursion containment, and cross-functional issue resolution. The position collaborates with Process Integration, Yield, Data Science, Global Manufacturing, and equipment suppliers to strengthen process monitoring, standardize Best Known Methods, and align inspection capability with future NAND technology nodes. Main Responsibilities Own the site-level RDA strategy and annual roadmap aligned with NAND Technology Development nodes. Lead analysis of experimental and production flows to detect, classify, and trend systematic and random defects. Establish, track, and report program health metrics, including baseline he

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Join our dynamic and innovative Team at Micron site in Vimercate, Italy! Department intro: Process and Device Technology Development (PDTD) is a core R&D organization within Micron’s Technology Development group responsible for developing the next generation of semiconductor memory technologies. The team drives innovation in process integration, device architecture, materials, characterization, modeling, and reliability for NAND products. Working closely with design, manufacturing, product engineering, and research partners, PDTD enables the technologies that become Micron’s future memory products. Position overview The mission of a device engineer working in Process and Device Technology Development team at Micron Technology Inc. is analyzing, modeling and improving the device electrical characteristics for the next generation NAND technologies in order to meet the performance and reliability specs required for NAND products within project timelines. Responsibilities: Contribute to device characterization and modeling for next generation NAND technologies. Define and execute new test flows to measure critical array electrical characteristics and define automatic electrical monitors for volume production. Understand NAND ce

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities include, but not limited to: ​ Key Responsibilities Develop systems to optimize operational performance across manufacturing platforms. Design, build, and deploy predictive models related to equipment utilization and performance enhancement. Analyze manufacturing data to identify bottlenecks and optimization opportunities for both short-term and long-term planning. Build and deploy LLM-based AI solutions to support fab operations, enabling smarter decision-making and improved operational efficiency. Collaborate closely with PMs, IT, and Core AI teams to drive cross-functional AI initiatives. Build interactive dashboards and visualizations to support data-driven decision-making. Work within the GCP environment for model training, deployment, and maintenance. Explore and implement MLOps, AutoML, and other advanced techniques to enhance model performance and reliability. Required Qualifications Master’s degree or above in Computer Science, Statistics, Engineering, or related fields 3&#43; years of experience in data science Proficient in Python, SQL, TensorFlow or other deep learning frameworks Skilled in data visualization tools Strong communication skills and experience in cross-functional collaboration </li

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As a key talent within High Bandwidth Memory (HBM) Product & System Engineering Media Health team, you will work together with a high performing team driving both intrinsic and extrinsic reliability test development and execution for Micron’s latest HBM products, both on DRAM and Interface die and a stacked product. Your responsibility is to drive extrinsic DPM reduction (Time 0 and Field DPM) and lead the intrinsic reliability charter, along with optimized Manufacturing Test Flow to meet critical KPI’s Quality, Cost and Cycle Time. You will work within the team to characterize the products from reliability aspect, identify the reliability gaps, working on root cause and resolution of qual and RMA failures pertaining to defectivity and intrinsic reliability margin and drive fab process improvement driven by the qual failures. Additionally, your team will also be the key person in frontend process conversion, where you will work with Fab, TD, GQ teams to establish robust business process for process conversions to facilitate yield improvements, DPM and Cost Reduction. You will collaborate across functions within and outside of HBM to meet both strategic and tactical objectives while continually maximizing the effectiveness of the HIG HBM PE organization. The future of HBM are exciting and dynamics.