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Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a mid- to senior-level Physical Design Engineer with a strong background in static timing analysis (STA). In this role, you will help converge multi-million-gate designs on advanced process nodes and partner with cross-functional teams through final signoff and tapeout. This role is hybrid , based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A physical design engineer with 8+ years of experience in STA, timing closure, and advanced-node design implementation. Experienced with timing flows, constraints, clocking, CDC, RDC, derates, uncertainties, guardbanding, and final signoff. Skilled in writing and debugging SDC constraints, creating ECOs, developing closure strategies, and analyzing worst-case corners. A strong collaborator and communicator who can drive results across distributed, cross-functional engineering teams. What We Need Drive timing convergence across blocks, partitions, sections, and top-level designs; generate and validate timing models and publish results. Analyze timing violations, develop and propagate fixes, debug timing-flow issues, and

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are at the heart of advanced DRAM node development, driving innovations from concept to high-volume production. Our team partners closely across Technology Development, Design, Quality, and Manufacturing to bring innovative memory technologies to life. If you’re excited about translating breakthrough ideas into real-world impact, you’ll find this work both challenging and rewarding. As a High Volume Manufacturing (HVM) Node Development Product Engineer, you will play a central role in introducing new DRAM nodes into production at the ID1 fab. This role connects development to manufacturing—owning yield ramp, cost efficiency, and quality improvements. You’ll collaborate cross-functionally to solve complex problems, improve product performance, and ensure successful technology transfer at scale. Responsibilities: Lead new node startup, qualification, yield ramp, and production readiness Guide development teams on process integration using deep technical insight Analyze yield data and electrical failures to drive measurable improvements Partner with Design, TD, Quality, and Test teams to resolve yield and performance issues Use statistical tools and lab analysis to identify root causes and optimize processes Minimum Qualifications: Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field Familiarity with DRAM architecture, operation, testing, and process integration Understanding of CMOS fundamentals and

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an Physical Design Engineer to lead cross-functional efforts to solve complex physical design challenges and develop end-to-end RTL-to-GDS methodologies across advanced nodes, with a strong focus on PPA and runtime improvements. The engineer will architect, integrate, and deploy AI/ML-driven solutions into production physical design flows, creating custom CAD tools and partnering with internal teams and EDA vendors to drive next-generation, ML-enabled capabilities. This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are BS in Electrical or Computer Engineering (or equivalent experience) with 5+ years in Physical Design CAD methodology at advanced nodes. Proven track record improving PPA and/or runtime on high-performance, low-power taped-out designs. Hands-on with industry-standard EDA tools (e.g., Fusion Compiler) across synthesis, P&R, STA, signoff, and hierarchical flows. Strong Python/Tcl and data skills, with interest or experience in ML frameworks (PyTorch, TensorFlow), and the ability to drive complex projects independent

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. You’ll lead physical verification closure (DRC, LVS, ERC, etc.), debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts. If you thrive in a fast-paced environment and enjoy solving complex challenges in cutting-edge silicon, we’d love to hear from you. This role is hybrid , based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure. A hands-on problem solver who excels at debugging and driving signoff through complex verification flows. A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces. A mentor and technical leader passionate about building efficient, manufacturable silicon. What We Need BS/MS in Electrical/Electronics Engineering (or related) with 7–14 years of hands-on CPU/IP/SoC physical verif

We are looking for a disciplined and dynamic, Lead System Engineer – compute blade and rack Validation to join our growing compute rack validation team. As a diligent leader in Systems Engineering, you will drive multiple aspects of validation throughout the life cycle of the program. In this high visibility position, you will be part of a leading team to innovate and improve system bring-up and enablement abilities, as well as silicon and system validation to deliver the highest quality, industry leading technologies to market. Your technical leadership skills, validation and debug expertise will be necessary towards product development, definition, root cause and resolution. Your agility and collaborative approach will be essential to work within System Validation & other engineering teams (System Architects, SoC and Rack FW etc). The technical leader will be driving keys areas of system validation including leading first silicon & system bring-up (nodes and rack level systems) - rack level systems and blades will be based of ARM server architecture. Candidate will be immersed in challenging system enablement work, system validation (end-to-end) methodology, tests development and execution as well as triage/debug of critical issues to meet critical program milestones at POR quality. The candidate will also be a key contributor to state-of-the-art HW and lab capabilities for Grapchore’s system engineering. The candidate should be able to work in a global environment while maintaining a synergetic culture. Primary Responsibilities: Lead the systemenablement (including first silicon and other FW components) to ensure system capabilities are brought up as per plan of record and system architecture spec. Drive organization wide methodology for Firmware integration and best known configuration (HW/FW/SW) usage model by leading the release of deployment ready solutions. Develop key methodologies, lab HW and system SW capabilit

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Technical Strategy & Innovation Define and execute the technical roadmap for Advanced DRAM Films development. Provide technical leadership across Epi, device films, hardmask technologies, HAR deposition, and diffusion processes. Drive innovative process solutions that enable future technology nodes while meeting manufacturability, yield, reliability, and cost objectives. Partner with Process Integration and cross-functional teams to resolve critical technology challenges. Leverage Artificial Intelligence to enhance problem solving across technical and logistical spaces. Organizational Leadership & Team Development Lead, coach, and develop a growing organization of engineers, technical leads, and future managers. Foster a culture of technical excellence, innovation, accountability, collaboration, and ownership. Develop talent through mentoring, succession planning, talent management, and strategic hiring. Create an environment that accelerates learning, encourages technical curiosity, and enables career growth for engineers at all levels. Drive high levels of team member engagement by cultivating an inclusive, supportive, and high-performing culture where employees feel valued, empowered, and connected to Micron's mission and business objectives. Champion employee development, recognition, feedback, and wellbeing

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Overlay Strategy, Roadmap & Technical Leadership Own the overlay roadmap including bond overlay technologies. Serve as the technical authority for overlay, defining overlay specifications, error budgets, mark strategies, technical signoff criteria, and scaling requirements for future technology nodes. Develop innovative overlay solutions that enable advanced bonding while meeting performance, yield, manufacturability, and scaling objectives. Drive advancement of overlay metrology, automation, process control, modeling, and analytics capabilities in partnership with Process and Metrology teams. Apply advanced analytics, Artificial Intelligence, simulation, and experimental methodologies to accelerate learning, identify root causes, and improve overlay performance. Technology Development & Problem Solving Lead simulation and experimental process development activities, balancing modeling with hands-on characterization and technology development. Develop and maintain overlay error budgets, validation plans, experiments, and technical assessments that connect process behavior to device and integration requirements. Solve complex overlay challenges involving alignment, distortion, deformation, process interactions, and bonded wafers. Translate technical findings into actionable process improvements, technology decisions, and roadmap recommendations. <

We are the GPU Communications Libraries and Networking team at NVIDIA. We deliver communication libraries like NCCL, NVSHMEM, UCX for Deep Learning and HPC. DL and HPC applications have a huge compute demand already and run on scales which go up to tens of thousands of GPUs. The GPUs are connected with high-speed interconnects (eg. NVLink, PCIe) within a node and with high-speed networking (eg. Infiniband, Ethernet) across the nodes. Communication performance between the GPUs has a direct impact on the end-to-end application performance; and the stakes are even higher at huge scales! We are looking for a technical leader to manage our NVSHMEM and UCX libraries. This is an outstanding opportunity to push the limits on the state-of-the-art and deliver platforms the world has never seen before. Are you ready for to contribute to the development of innovative technologies and help realize NVIDIA's vision? What you will be doing: Lead, mentor, and grow your library engineering team and be responsible for the planning and execution of projects as well as the quality, and performance of your libraries. This is a technical leadership role so you will participate in feature design and implementation. Interact with internal and external partners and researchers to understand their use cases and requirements. Collaborate with engineering teams, program and product management, and partners to define the product roadmap. Continuously review and identify improvement opportunities in established processes, infrastructure, and practices to ensure the teams are executing in the most efficient and transparent manner. What we need to see: 10&#43; overall years of experience in the software industry with specialization in HPC networking or system software. 4&#43; years of management experience. BS, MS, or Ph.D. in C

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