Performance Architect Jobs

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. About the Role EnCharge AI is seeking a highly skilled and experienced AI Compiler Engineer to spearhead the efforts in developing and optimizing graph compilers tailored to cutting-edge AI and ML workloads. You will collaborate with hardware architects, and AI researchers to enhance performance, optimize computation graphs, and enable efficient model deployment on EnCharge’s Inference Accelerators. Responsibilities Architect, design, and implement optimizations for AI model execution on graph compilers to improve performance, reduce latency, and maximize hardware utilization. Work closely with ML researchers, hardware engineers, and software developers to design and deploy AI models, understanding and addressing hardware-specific challenges. Work on performance optimizations for neural network models, such as layer fusion, operator fusion, and graph-level transformations. Develop compiler optimizations and passes that convert high-level AI models (e.g., from TensorFlow, PyTorch) into intermediate representations (IR). Implement parsing, semantic analysis, and IR generation for deep learning frameworks. Research and integrate the latest advancements in compiler design, ML model optimizations, and hardware acceleration into graph compilers. Provide leadership, mentorship, and technical guidance to a team of engineers focused on graph compiler optimizations. Qual

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Senior Emulation Engineer Location: India - Remote Job Description: At EnCharge AI, we are building the next generation of AI compute silicon — purpose-built for high-performance, low-power, and scalable AI inference. As an Emulation Engineer, you will play a critical role in validating complex AI accelerator architectures on emulation platforms before tape-out. This position is ideal for someone passionate about bridging the gap between hardware and software in fast-paced, deep tech environments. Responsibilities: • Set up and maintain Siemens Veloce emulation and prototyping platforms • Adapt SoC designs for Emulation and Prototyping • Develop and debug emulation testbenches and system-level environments • Support pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-up and validation. • Collaborate with design and verification teams to isolate design issues and accelerate debug. • Optimize performance of the emulation workloads and reduce turnaround time. • Work with firmware/software teams to enable use of emulators for OS and driver testing. Required Background: • BS/MS/Ph.D. in EE, CS, or related field with 7+ years of SoC design experience. • Experience with emulation platforms (Veloce, Palladium, or ZeBu) and FPGA-based prototyping systems (proFPGA, HAPS, or Protium) • Experience with emula

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Physical Design Engineer (2-4 Years Experience) We are looking for a high-caliber Physical Design Engineer to join our fast-paced startup team. This role is designed for "top 1%" talent—engineers from tier-1 universities (IIT/NIT/BITS or equivalent) who possess a relentless "go-getter" attitude and the critical thinking skills required to solve complex, next-generation silicon challenges. If you are eager to move beyond standard digital flows into the future of AI-driven automation , this is your playground. Key Responsibilities End-to-End Ownership: Drive RTL-to-GDSII implementation, including floorplanning, placement, CTS, routing, and physical verification (LVS/DRC/ERC). Performance Optimization: Execute high-performance design closure focusing on PPA (Power, Performance, Area) targets in advanced process nodes ( 3nm or below) Static Timing Analysis (STA): Perform comprehensive timing closure, including signal integrity, crosstalk analysis, and CPPR (Common Path Pessimism Removal) optimization. Power Integrity: Conduct IR-drop analysis (Static/Dynamic) and EM (Electromigration) checks to ensure robust power delivery. Innovation: Develop and integrate AI/ML-based automation scripts to optimize the physical design flow and reduce turnaround time. Qualifications &am

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Staff/Senior Staff Physical Design Floorplan & PDN Lead Experience: 10–14 Years Location: Bangalore/2 days to work Department: RTL-to-GDSII / Physical Implementation Role Overview We are seeking a high-caliber Staff or Senior Staff Physical Design Engineer with a specialized mastery of Floorplanning and Power Delivery Network (PDN) design. You won’t just be pushing buttons; you will be the architectural bridge between RTL/Systems and the final GDSII. This role requires a visionary who understands how a single floorplan decision ripples through the entire PPA (Power, Performance, Area) spectrum. As a technical lead, you will own the chip-top floorplan for complex, large-scale SoCs or Sub-chips, driving strategies that balance aggressive performance targets with robust power integrity. Key Responsibilities Architectural Floorplanning: Lead chip-level floorplanning, including macro placement, pin assignment, and partition definition for multi-million gate designs. Strategic PDN Design: Architect and implement complex Power Delivery Networks. You will define the metal stack usage and grid density to support high-performance cores while minimizing routing congestion. EMIR Mastery: Perform exhaustive IR-drop (Static/Dynamic) and Electromigration (EM) analysis. You must be able to diagnose root causes and propose ar

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Job Title: Staff/ Senior Staff Physical Design Engineer (Technical Lead) Experience: Staff 8-10 years Senior Staff 11-13 years Location: Bangalore Hybrid/Remote or Remote in India The Role We are seeking a high-impact Staff/ Senior Staff Physical Design Engineer to serve as a Technical Lead for our next-generation silicon products. This is a "player-coach" role designed for a versatile expert who is equally comfortable architecting a convergence strategy as they are mentoring a small team of engineers. You will own the physical delivery of a major sub-chip or complex block, pushing the absolute limits of PPA (Power, Performance, Area) . As a Staff/Senior Staff lead, you are expected to be the "anchor" of the project—assertive in your decision-making, highly analytical in your debugging, and adept at managing stakeholders to ensure we hit our tape-out milestones without compromise. Key Responsibilities Technical Leadership: Lead a small team of PD engineers, providing technical direction, workload management, and architectural oversight for a sub-chip or partition. SOC clocking , FEV/VCLP specialized skills are preferred. Complex Block/Sub-chip Ownership: Take personal hands-on ownership of the most critical, high-congestion, or timing-critical blocks in the desi

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Job Title: Senior Physical Design Engineer Experience: 4–7 Years Focus: Block-Level RTL-to-GDSII & PPA Optimization Location: Bangalore Hybrid The Role We are looking for a high-energy, technically curious Physical Design Engineer to join our advanced silicon team. This isn't a role for someone who wants to just "push buttons" on a vendor flow. We need a driver—someone with 4–6 years of experience who has lived through the trenches of quality tape-outs and is hungry to take full ownership of complex partitions. You will be expected to work with a high degree of independence, using your analytical skills to bridge the gap between a standard recipe and a world-class PPA result . You should be comfortable following expert lead direction while maintaining the "question the status-quo" mindset when you see a more efficient path. Key Responsibilities Partition Ownership: Lead the physical implementation of complex blocks from Synthesis and Floor-planning through to CTS, Routing, and Sign-off. PPA Recipe Development: Don't just run the flow—optimize it. You will perform deep-dive analysis on timing paths, power profiles, and congestion to derive custom optimization strategies. Automation-First Mindset: Use Tcl and Python to automate repetitive tasks, build custom analysis scripts, and enhan

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Job Title: Principal Physical Design Engineer (RTL-to-GDSII) Experience: 14+ Years Technology Focus: Sub-5nm (3nm/2nm) Location: Bangalore Hybrid The Vision We are seeking a Principal Physical Design Engineer who thrives on complexity and rejects the "black box" approach to EDA tools. This role is for a First Principles thinker who questions the status quo. If a standard flow isn't yielding the desired PPA (Power, Performance, Area), you dive into the PDK, the tool algorithms, and the methodology to find a better way. You are responsible for transforming raw RTL into world-class silicon by eliminating systemic bottlenecks and building a scalable, predictable path to GDSII. Key Responsibilities Full-Flow Ownership: Lead the implementation of massive, high-speed blocks/SoCs from Synthesis through Sign-off using the Cadence Digital Suite . PPA Optimization: Push the theoretical limits of the PDK and tools. You will analyze and optimize the interplay between library cells, metal stacks, and tool engines to squeeze out every millivolt and picosecond. Methodology & Scalability: Build and refine a "Push-Button" style execution methodology that is robust, repeatable, and minimizes manual "human-in-the-loop" iterations. Cross-Functional "Left-Shift": Collaborate with RTL, Architecture, and DFT te

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Job Description : Lead DFT Engineer (Edge Computing) Developing silicon for Edge Computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments. As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment. Key Responsibilities Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST. Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers. Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory /Logic BIST. Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact as well as timing analysis . Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time. Technical Requirements Experience: 12+ years in DFT, with at least 2 years in a leadership or principal role. Tools: Mastery of industry-standard

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. About the Role EnCharge AI is seeking a highly skilled Device Driver Engineer to design and implement high-performance driver stack for our cutting-edge AI accelerator hardware. In this role, you will work closely with hardware, firmware, and AI software teams to develop low-latency, high-bandwidth communication between the host system and AI accelerator. Responsibilities Develop, optimize, and maintain Linux/Windows PCIe device drivers for AI accelerators. Implement low-level hardware interactions, DMA, memory management, and interrupt handling. Work on driver optimizations to reduce latency and improve throughput for AI workloads. Debug and troubleshoot PCIe protocol, kernel panics, crashes, and performance bottlenecks. Collaborate with hardware, firmware, and AI software teams to define driver interfaces. Ensure compliance with PCIe standards (Gen4/Gen5), SR-IOV, BAR memory mapping, and IOMMU. Support virtualization (VFIO, SR-IOV, DPUs) and containerized environments (Kubernetes, Docker, etc.). Develop tools for profiling, debugging, and monitoring driver performance. Contribute to open-source kernel modules if applicable. Qualifications Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field. 3+ years of experience in device driver development for Linux and/or Windows. Strong experience with PCIe-based hardware, including BAR

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. About the Role EnCharge AI is looking for an Embedded SW Engineer to develop the firmware for our Edge AI processors. The candidate must possess an excellent understanding of computer architecture and operating system concepts including, but not limited to, memory management, virtualization and PCIe address space. The role includes designing and developing the core Firmware for various parts of the SOC. The candidate must possess strong communication skills to interface with Runtime, Architecture and H/W teams. Responsibilities Develop the critical pieces of EAI Firmware used to deploy inference jobs on EAI processors Validate different IP blocks on the SOC Evaluate and integrate third-party device drivers to interface with EnCharge’s SW stack Work closely with the Runtime, Hardware and Architecture teams define the driver architecture Qualifications Bachelors in EE/CS Advanced programming skills in C/C++ for operating system kernel & systems development Understanding of RISC-V architecture is a plus Exposure to PCIe BAR and IOMMU architecture Exposure to virtualization and hypervisor technologies Deep understanding of operating systems concepts, data structures, x86-64 and accelerator architectures Experience with low-level debug tools as well as emulators and simulators Experience running, analyzing, and tuning system performance benchmarks Excellent verb

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. About the Role EnCharge AI is seeking an AI Runtime Engineer to develop and optimize the execution stack for our next-generation AI accelerator. In this role, you will work on low-latency, high-performance runtime software that enables efficient execution of deep learning models on specialized hardware. You will collaborate with hardware, compiler, and AI framework teams to deliver optimized AI inference and training performance across cloud and edge environments. Responsibilities Develop and optimize the AI runtime software stack for executing deep learning workloads on AI accelerators. Implement task scheduling, memory management, and kernel execution strategies for efficient computation. Optimize data movement between host and device using PCIe, DMA, shared memory. Design and implement high-performance APIs for AI Inference frameworks such as OpenVino, ONNX Runtime, vLLM Work on graph execution optimizations, including kernel fusion, pipelining, tensor tiling, and caching. Integrate runtime components with AI compilers (LLVM, MLIR, XLA, TVM) for optimized execution. Ensure scalability and reliability of the AI runtime for cloud-based and edge AI deployments. Qualifications Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field. 3+ years of experience in developing low-level runtime software for AI accelerators, GPUs, or

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. About the Role EnCharge AI is seeking a highly skilled and experienced AI Compiler Engineer to spearhead the efforts in developing and optimizing graph compilers tailored to cutting-edge AI and ML workloads. You will collaborate with hardware architects, and AI researchers to enhance performance, optimize computation graphs, and enable efficient model deployment on EnCharge’s Inference Accelerators. Responsibilities Architect, design, and implement optimizations for AI model execution on graph compilers to improve performance, reduce latency, and maximize hardware utilization. Work closely with ML researchers, hardware engineers, and software developers to design and deploy AI models, understanding and addressing hardware-specific challenges. Work on performance optimizations for neural network models, such as layer fusion, operator fusion, and graph-level transformations. Develop compiler optimizations and passes that convert high-level AI models (e.g., from TensorFlow, PyTorch) into intermediate representations (IR). Implement parsing, semantic analysis, and IR generation for deep learning frameworks. Research and integrate the latest advancements in compiler design, ML model optimizations, and hardware acceleration into graph compilers. Provide leadership, mentorship, and technical guidance to a team of engineers focused on graph compiler optimizations. Qual

About the Role In this role, you will operate, scale, and optimize multi-petabyte storage systems purpose-built for the world’s largest AI training and inference workloads. You’ll manage and scale high-performance parallel filesystems and object stores, evaluate and integrate cutting-edge technologies such as Vast, Weka, Ceph, and Lustre, and solve the complex engineering challenges of operating at extreme throughput, low-latency data paths, and massive cluster-scale storage operations. You will also build Kubernetes-native storage operators and self-service platforms that provide automated provisioning, strict multi-tenancy, performance isolation, and quota enforcement at cluster scale. Day-to-day, you’ll optimize end-to-end data paths for 10-50 GB/s per node, design multi-tier caching architectures, implement intelligent prefetching and model-weight distribution, and tune parallel filesystems for AI workloads. Responsibilities Architect and implement the technical strategy and storage roadmap for Together AI, driving high-performance architectural decisions as we scale our GPU fleet. Engineer and scale multi-petabyte AI/ML storage systems by integrating Vast, Weka, and Ceph while executing deep cost optimization through automated tiering and lifecycle policies. Develop intelligent caching and tiered storage architectures to achieve extreme IOPS and cluster-wide throughput at GPU scale for training and inference workloads. Tune storage isolation at the L2/L3 network layers to ensure secure, production-grade multi-tenancy for storage clients. Code Kubernetes storage operators and controllers to enable automated provisioning, self-service abstractions, and quota enforcement. Engineer end-to-end data paths to achieve 10+ GB/s per GPU node; architect multi-tier caching for model weights and datasets; tune parallel filesystems using advanced profiling; and scale storage infrastructure across thousands of nodes. Optimize end-to-end data paths through advanced

About the Role In this role, you will operate, scale, and optimize multi-petabyte storage systems purpose-built for the world’s largest AI training and inference workloads. You’ll manage and scale high-performance parallel filesystems and object stores, evaluate and integrate cutting-edge technologies such as Vast, Weka, Ceph, and Lustre, and solve the complex engineering challenges of operating at extreme throughput, low-latency data paths, and massive cluster-scale storage operations. You will also build Kubernetes-native storage operators and self-service platforms that provide automated provisioning, strict multi-tenancy, performance isolation, and quota enforcement at cluster scale. Day-to-day, you’ll optimize end-to-end data paths for 10-50 GB/s per node, design multi-tier caching architectures, implement intelligent prefetching and model-weight distribution, and tune parallel filesystems for AI workloads. Responsibilities Architect and implement the technical strategy and storage roadmap for Together AI, driving high-performance architectural decisions as we scale our GPU fleet. Engineer and scale multi-petabyte AI/ML storage systems by integrating Vast, Weka, and Ceph while executing deep cost optimization through automated tiering and lifecycle policies. Develop intelligent caching and tiered storage architectures to achieve extreme IOPS and cluster-wide throughput at GPU scale for training and inference workloads. Tune storage isolation at the L2/L3 network layers to ensure secure, production-grade multi-tenancy for storage clients. Code Kubernetes storage operators and controllers to enable automated provisioning, self-service abstractions, and quota enforcement. Engineer end-to-end data paths to achieve 10+ GB/s per GPU node; architect multi-tier caching for model weights and datasets; tune parallel filesystems using advanced profiling; and scale storage infrastructure across thousands of nodes. Optimize end-to-end data paths through advanced

Job Overview: We are seeking a high-caliber Rust Systems Engineer to design, build, and optimize high-throughput, low-latency backend systems and infrastructure. In this role, you will go beyond web APIs—tackling low-level performance bottlenecks, complex state management, parallel compute algorithms, and concurrent data processing pipelines. If you thrive on deterministic memory management, zero-cost abstractions, and writing safe, blazingly fast concurrent systems, this role is for you. Key Responsibilities: High-Performance Architecture: Design and implement zero-cost, high-throughput, low-latency engine components and data processing pipelines in Rust. Concurrent & Thread-Safe Systems: Build thread-safe, lock-free, or fine-grained locked data structures and state machines capable of scaling across multi-core architectures without race conditions. Priority & Real-Time Threading: Design custom thread pools, task schedulers, and execution queues with priority-based task scheduling and resource allocation controls. Algorithmic Optimization: Implement complex computational logic, including high-efficiency recursive algorithms, tail-call optimizations, and dynamic cache-friendly data structures. Resource & Memory Management: Leverage Rust’s ownership model, lifetime annotations, custom allocators, and non-blocking I/O to achieve predictable low-latency profiling (minimizing allocations and cash misses). System Profiling & Benchmarking: Conduct continuous benchmarking (criterion), flame graph analysis, memory profiling (Val grind/heap track), and CPU SIMD/vectorization optimizations. Key Skills: Core Rust & Functional Programming: Advanced Rust Mastery: Deep experience with Rust internals (stdsync, stdcell, custom Drop, unsafe Rust boundaries, and macro systems). Closures & Higher-Order Functions: Mastery of Rust’s functional traits (Fn, FnMut, FnOnce), capturing environments, move semantics within closures, and passing unboxed closures for zero