Performance Fitter Jobs

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a highly skilled and motivated Senior Design Verification Engineer to join our team. In this role, you will be responsible for the end-to-end verification of our IOMMU (Input/Output Memory Management Unit) IP. You will play a critical role in ensuring the functional correctness and performance of the design, taking ownership of the verification process right from the initial specification understanding down to final coverage closure. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You have hands-on experience in ASIC or SoC verification using SystemVerilog and UVM. You enjoy debugging complex design and verification issues and working closely with cross-functional teams. You’re comfortable building verification environments from scratch and driving coverage closure. You have familiarity with standard bus protocols and modern verification tools. What We Need Experience owning block or subsystem-level verification from test planning to sign-off. Strong understanding of constrained-random verification, coverage analysis, and regression debugging. Familiarity with proto

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. As a Datacenter Liquid Cooling Architect, you will define, design, and architect next-generation liquid cooling infrastructure for Tenstorrent’s large-scale AI training and inference clusters. You will partner with systems engineering, mechanical engineering, software, and cross-functional design teams to develop chassis-, rack-, and cluster-scale cooling solutions, including CDU integration, telemetry and control, leak detection, and resilient operating strategies. This role will help shape reliable AI datacenter architectures and deployments for both internal and external customers. This role is on-site, based out of Toronto, Canada, Austin, Texas or Santa Clara, California. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A datacenter and system thermal design professional with 10+ years of experience architecting cooling infrastructure for complex computing environments. An experienced liquid cooling architect who can design chassis- and rack-scale solutions for large AI training and inference clusters. A systems thinker who understands how mechanical, electrical, software, facility, and systems engineering decisions come toge

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a mid- to senior-level Physical Design Engineer who will contribute to the physical design of high-performance chips for industry-leading AI/ML architectures, spanning implementation from synthesis through tapeout. You will partner with front-end and physical design engineers to optimize floorplanning, timing, power, performance, and area across multiple IPs. Along the way, you will build end-to-end ASIC expertise while learning from experienced engineers across the chip development process. This role is hybrid , based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An engineer excited to work on high-performance designs for industry-leading AI/ML architectures. A collaborative problem solver who enjoys working with experienced engineers across ASIC disciplines. Grounded in logic design fundamentals and gate- and transistor-level implementation. Curious about how early architectural and RTL decisions shape physical implementation and final chip quality. What We Need A BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a relat

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. As a PCB Power Design Engineer, you will design and optimize power distribution systems for Tenstorrent’s next-generation AI accelerator cards, balancing performance, area, cost, and reliability. You will contribute across the full power design lifecycle, from component selection and simulation through board bring-up, validation, debugging, and production readiness. Working closely with hardware, firmware/software, thermal, mechanical, and validation teams, you will help deliver robust power architectures for high-performance AI systems. This role is hybrid, based out of Toronto, Canada. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An electrical engineer with experience designing, analyzing, and debugging power distribution systems for high-performance or high-power products. A hands-on engineer who enjoys moving from schematics and simulations into lab bring-up, testing, troubleshooting, and design validation. A systems-oriented collaborator who can work effectively across hardware design, firmware/software, thermal, mechanical, and validation teams. A detail-oriented problem solver who balances electrical performance, power integr

End to end responsible for: • forward-looking financial planning, scenario analysis and performance insights to improve returns and predictability. • revenue, collections, margin and cashflow forecasting with risk visibility and mitigation actions. • decision support for pricing, schemes, capital allocation and portfolio trade-offs using analytics. • standardized business review cadence and KPI governance with high data quality. Source: Adani Group | Job ID: 58733

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a mid- to senior-level Physical Design Engineer with a strong background in static timing analysis (STA). In this role, you will help converge multi-million-gate designs on advanced process nodes and partner with cross-functional teams through final signoff and tapeout. This role is hybrid , based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A physical design engineer with 8+ years of experience in STA, timing closure, and advanced-node design implementation. Experienced with timing flows, constraints, clocking, CDC, RDC, derates, uncertainties, guardbanding, and final signoff. Skilled in writing and debugging SDC constraints, creating ECOs, developing closure strategies, and analyzing worst-case corners. A strong collaborator and communicator who can drive results across distributed, cross-functional engineering teams. What We Need Drive timing convergence across blocks, partitions, sections, and top-level designs; generate and validate timing models and publish results. Analyze timing violations, develop and propagate fixes, debug timing-flow issues, and

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We’re looking for a Field Application Engineer who’s wired for AI/ML, fluent in real-world problem-solving, and excited to build with the people actually using what we make. You will collaborate closely with the sales team and enterprise customers, leveraging your deep technical knowledge in AI to drive the adoption of our products and solutions. This is a customer-facing role that requires both technical expertise and excellent communication skills to convey complex technical concepts to non-technical stakeholders. This role is remote or hybrid based out of Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You’ve lived in the AI/ML trenches, whether as a field engineer, a solutions architect, or the one tapped in when things needed to “just work.” You speak both machine and human. Whether it’s a researcher or a skeptical executive, you know how to break things down and bring them to life. You’re fired up about generative models, LLMs, and the edge of what’s possible when software meets purpose-built silicon. Work directly with customers in meetings, presentations, and workshops to understand their technical challe

NVIDIA is seeking a world-class computer architect to contribute to the development of future high-performance computing systems, with a focus on enhancing the power-constrained performance of the hardware. Ideal candidates will have a strong track record of understanding and analyzing memory systems architecture to improve performance per watt (perf/W) and performance per millimeter (perf/mm). A broad perspective across the field of computer architecture and depth in the area of power, performance, and area (PPA) analysis is highly desirable. NVIDIA has pioneered programmable GPUs and the CUDA language and is a world leader in high-performance computing technology, with aggressive plans for future processors. This position offers the opportunity to have a real impact in a fast-moving, technology-focused company. What you will be doing: Develop innovative high-performance processor and system architectures, focusing on the memory system and energy efficiency. Develop architecture and micro-architecture features to improve the state-of-the-art in GPU memory systems, optimizing along the axes of perf/W, perf/mm, and perf/$. Develop and enhance architecture prototype models for power and noise analysis. Participate in performance and power simulation of features to analyze, define, and improve energy per byte. Analyze benchmarks, application workloads, and performance/power simulation and emulation results to identify areas for architecture optimizations. Debug power, performance, and functional issues with high-level models, RTL simulation and emulation, silicon, and systems. Collaborate with outside partners on system infrastructure. What we want to see: 10+ yrs of experience in CPU/GPU architecture, memory systems design with a focus on energy efficiency in the system. Bachelor

End to end responsible for: • HR business partnering for SBU by executing workforce plans, performance cycles and engagement programs locally. • first-line ER support, grievance handling and compliance readiness with timely escalations to IR/ER specialists. • employee lifecycle execution with GCC‑HR for transactions, ensuring smooth onboarding, movements and exits. • local administration coordination to meet site workplace and employee needs within standards. Source: Adani Group | Job ID: 58540

Participant Recruitment Partner/Sourcer 3 month FTC with the opportunity to extend - Open to candidates based in US/Mexico Compensation - Base Salary + monthly performance bonus potential based on performance NB - these roles are high priority - therefore we are prioritisitng candidates who can commence employment in the next 2 weeks Team: Human Data Prolific Prolific is not just another player in the AI space – we are the architects of the human data infrastructure that's reshaping the landscape of AI development. In a world where foundational AI technologies are increasingly commoditized, it's the quality and diversity of human-generated data that truly differentiates products and models. The role As a Participant Recruitment Partner, you will play a pivotal role in continuing the growth of Prolific's specialised participant pools. You’ll act as a key enabler for the evergreen expansion of our expert network, as well as working closely with delivery teams to support targeted participant-resourcing based on our customers needs.This role demands a hands-on approach to high volume participant identification, attraction, and engagement, as well as cross-functional collaboration to meet the demands of both internal stakeholders and external clients What you’ll be doing in the role Drive the identification, attraction, and engagement of top-tier, highly qualified specialist participants, building and maintaining Prolific’s world-class participant pool. Act as a trusted partner for client-specific AI delivery teams, serving as the primary point of contact for all recruitment-related operations and ensuring seamless collaboration. Deliver exceptional results on bespoke client projects, consistently meeting or exceeding ambitious project goals. Maintain and elevate the quality, diversity, and readiness of Prolific’s participant pools, optimising for customer needs and high-impact outcomes. Design and manage robust verification processes for domain experts

Reolink , a leader in intelligent visual technology for homes and businesses, was founded in 2009 by a group of engineers with a strong commitment to and passion for smarter security solutions. Our products are now trusted by millions of users across more than 110 countries and regions worldwide. Building on this trust, we continue expanding our presence and bringing our innovations to more markets around the globe. Reolink remains committed to delivering advanced, reliable, and user‑centric solutions that empower people to protect what matters most. 5 Work Days Per Week Relocate Near Tai Seng MRT in August 2026 Medical Benefits Provided Entitled to Yearly Bonus & Performance Bonus Requirements Bachelor’s degree or higher, preferably in Marketing, Advertising, Statistics, or a related discipline. Minimum 5 years of hands‑on experience in advertising operations; experience in 3C, e‑commerce, internet products, or cross‑border advertising is a strong advantage. Proficiency in managing at least two major advertising platforms, with strong data analysis skills and familiarity with Excel/Google Sheets and analytics tools. Strong strategic thinking and results‑oriented mindset, with the ability to manage multiple campaigns and projects in a fast‑paced environment. Excellent communication and collaboration skills. Experience in team leadership or agency management is an advantage. Key Responsibilities Develop and execute annual advertising strategies, manage monthly advertising budgets, and ensure ROI and performance targets are consistently achieved. Oversee day‑to‑day operations across major advertising platforms (including Meta Ads, Google Ads, TikTok Ads, and Ocean Engine), covering campaign setup, optimization, A/B testing, and performance monitoring. Conduct in‑depth analysis of campaign performance and key metrics; prepare regular performance reports and recommend optimization initiatives to reduce CPA and improve conversion rates. Collaborate closel

Role Purpose: At Jumio, the Software Engineer II (QA) will focus on ensuring the quality and performance of highly scalable web and backend applications. In this role, you will design and implement automated tests for web (Playwright/Selenium) and API-based solutions, leveraging your knowledge of Java or JavaScript. Collaborating closely with development and product teams, you will ensure Jumio's products meet the highest standards of quality and reliability. You’ll have an opportunity to learn and grow in a fast-paced environment while exploring new tools and methodologies. A problem-solving mindset, willingness to innovate, and attention to detail will make you successful in this role. T-Shaped Engineering Expectation: As part of Jumio’s engineering culture, you will adopt a T-shaped engineering approach. In addition to developing expertise in test automation and quality engineering, you will collaborate across the development lifecycle, including understanding software architecture, contributing to design discussions, and ensuring robust and scalable test solutions. Role Value: This role is critical to ensuring the reliability, scalability, and security of Jumio’s products. By building and maintaining automated testing frameworks, you will enable faster releases and higher confidence in the quality of our software. Example Responsibilities: Develop, maintain, and execute automated test scripts for web applications using Playwright, Selenium, or similar automation frameworks. Create and execute API test suites using tools such as Postman, REST Assured, or equivalent testing frameworks. Design and execute functional, regression, integration, and exploratory test cases based on business and technical requirements. Validate application functionality, backend services, APIs, and data flows across different environments. Identify, document, track, and verify defects, working closely with developers to ensure timely resolution. Execute automated test suites as part of C

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an Physical Design Engineer to lead cross-functional efforts to solve complex physical design challenges and develop end-to-end RTL-to-GDS methodologies across advanced nodes, with a strong focus on PPA and runtime improvements. The engineer will architect, integrate, and deploy AI/ML-driven solutions into production physical design flows, creating custom CAD tools and partnering with internal teams and EDA vendors to drive next-generation, ML-enabled capabilities. This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are BS in Electrical or Computer Engineering (or equivalent experience) with 5+ years in Physical Design CAD methodology at advanced nodes. Proven track record improving PPA and/or runtime on high-performance, low-power taped-out designs. Hands-on with industry-standard EDA tools (e.g., Fusion Compiler) across synthesis, P&R, STA, signoff, and hierarchical flows. Strong Python/Tcl and data skills, with interest or experience in ML frameworks (PyTorch, TensorFlow), and the ability to drive complex projects independent

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a highly technical Senior Staff/Principal Engineer to lead the porting and enablement of critical AI workloads. You will be a primary driver in migrating compute workloads to RISC-V architectures, ensuring our hardware is optimized for real-world application performance. The ideal candidate has a strong background in DevOps, workload porting, or application enablement . While this is an individual contributor role at its core, you will have the opportunity to grow and lead a small, specialized team over time as our workload migration efforts scale. This role is remote, based in the United States or Australia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A Technical Catalyst: You thrive on the challenge of driving AI hardware porting to RISC-V and making complex software stacks run efficiently on new hardware. Systems Expert: You possess deep knowledge of system software, compilers, or low-level OS internals. You are an expert in ARM or x86 environments and are ready to apply those skills to the RISC-V frontier. A Project Driver: You have the technical authority to lead the implementation of a compute migration to RISC-V through

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team to define and implement RTL for high-performance CPUs. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experienced in CPU microarchitecture with expertise in Rename, Scheduler, ROB, Load Store, Branch Prediction, Cache or Datapath. Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis. Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments. Background in microarchitecture definition, design specification, and performance-driven trade-off analysis. What We Need Own RTL design and microarchitecture development for a portion of a CPU block of a high-performance RISC-V CPU. Collaborate closely with DV, PD, and performance engineers to meet functional, timing, and power goals. Use innovative techniques to optimize power, performance, and