Physical Security Manager Jobs

CPU Physical Design Engineer — India, Bangalore. Apply via Workday.

CPU Physical Design Engineer — India, Bangalore. Apply via Workday.

SoC Physical Design Engineer, Senior Member of Technical Staff (SMTS) — 2 Locations. Apply via Workday.

Digital Physical Implementation and Integration Engineer — San Jose, CA. Apply via Workday.

Principal Physical Design — Boise, ID - Main Site. Apply via Workday.

Staff Physical Design Engineer-DPG-LPDDR — Hyderabad - Phoenix Aquila, India. Apply via Workday.

CPU Physical Design Engineer — Texas, Austin. Apply via Workday.

Job Details: Job Description: The Role and Impact As a Physical Design Engineer, you will play a critical role in driving the development of cutting-edge technologies at Intel. You will work hands-on to deliver high-performance physical designs, ensuring the successful integration of advanced semiconductor technologies. Your work will directly impact Intel's product innovation, addressing complex challenges in power, performance, and area optimization to shape the future of computing architectures. From synthesis to sign-off, your contributions will enable Intel to meet ambitious design goals and deliver transformative solutions to the market. Business Group This role is part of Intel's Corporate Technology Office (CTO), a dynamic group dedicated to advancing the company's technological leadership and innovation. The group focuses on developing foundational technologies, architectures, and methodologies that drive Intel's product roadmap and enable breakthrough computing solutions. Collaborating with cross-disciplinary teams, the CTO plays a pivotal role in delivering impactful designs that support Intel's broader mission of creating world-changing technology. Key Responsibilities - Drive RTL-to-GDS design convergence using advanced synthesis and place-and-route tools targeting performance, power, and area (PPA) goals. - Deliver block-level physical design, including closure of backend flows, electrical requirements, and enhancing silicon yield. - Collaborate with CAD and physical design methodology teams to adopt industry-leading tools and optimizations for custom designs. - Execute physical implementation tasks such as floor planning, bus/pin placement, power/clock distribution, congestion analysis, timing closure, IR drop analysis, and physical verification. - Debug timing, EM/IR, LVS, and DRC violations, and driv

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Design Technology Co-Optimization (DTCO) team works at the intersection of process technology, standard cell architecture, and design implementation to optimize power, performance, and area (PPA) for advanced memory products. The team collaborates closely with standard cell library, RTL, and physical design engineers to evaluate design tradeoffs and develop methodologies that improve silicon outcomes. As a DTCO Intern, you will gain hands-on experience assessing and optimizing PPA at the standard cell and logic block level. You will use industry-standard place-and-route tools and AI-enabled automation techniques to implement, benchmark, and optimize logic blocks while developing practical skills in physical design, timing closure, and design analysis. Responsibilities Implement standard cell logic blocks using industry-standard physical design tools, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization activities focused on PPA assessment. Analyze and benchmark power, performance, and area across standard cell libraries and logic block configurations, identifying opportunities for improvement. Perform static timing analysis (STA), investigate setup and hold timing violations, and support timing closure activities. Execute physical verification checks, including DRC, LVS, and IR-drop analysis, and assist with resolving design issues. Leverage Generative AI, AI Assistants, and Agentic AI solutions to automate data collection, reporting, comparison, and w

Senior Scientist – Physical AI for Surgical Robotics (Cambridge, MA) — Cambridge (US), Massachusetts, United States. Apply via Workday.

Intern - YE Physical Failure Analysis Engineer — Boise, ID - Main Site. Apply via Workday.

Staff Digital Physical Implementation and Integration Engineer — San Jose, CA. Apply via Workday.

Lead Substation Physical Engineer — Atlanta, GA. Apply via Workday.

Engineer CE PYE (Physical Failure Analysis/Fault Isolation) — 2 Locations. Apply via Workday.

HBM SoC Physical Design Engineer — Richardson, TX. Apply via Workday.