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About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. Role Overview We are seeking an experienced ASIC Package Signal Integrity / Power Integrity Engineer to drive electrical architecture, modeling, optimization, and validation for the most advanced AI/HPC silicon and package design. This role focuses on high-speed SerDes and memory channel architecture, advanced 2.5D/3D package SI/PI, substrate to package co-design, power-delivery-network optimization, electromagnetic modeling, and simulation-to-measurement correlation. The ideal candidate has strong hands-on experience with high-speed channel and PDN analysis across ASIC packages, interposers, substrates, and power-delivery structures, and can translate simulation results into practical design requirements for interposers and package substrate design optimization. The engineer will work closely with ASIC, package, system, mechanical, thermal, power, and silicon validation teams from early architecture and feasibility studies through production bring-up. In this role you will Own SI/PI architecture and analysis for advanced AI ASIC packages from early feasibility studies through production. Develop and optimize high-speed electrical channels for 200G/400G SerDes, PCIe, HBM, DDR, and chiplet/die-to-die interfaces. Perform package, interposer and substrate modeling using 2D/3D electromagnetic solvers. Define and optimize package stack-ups, transmission-line structures, via transitions, breakout structures, return paths, ground shielding, bump maps, and ball maps based on SI/PI re

FE CPIE PI Principal/Staff Engineer — 2 Locations. Apply via Workday.

FE CPIE PI MTS — 2 Locations. Apply via Workday.

F15 Advanced Technology Japan PI Device Engineer — Hiroshima - Fab 15, Japan. Apply via Workday.

MSH PDE PI MANAGER — Fab 10A, Singapore. Apply via Workday.

FE CPIE PI Principal/Staff Engineer — Boise, ID - ID1. Apply via Workday.

OMT TECHNOLOGY DEVICE and PI — Taichung - Fab 16, Taiwan. Apply via Workday.

OMT TECHNOLOGY DEVICE and PI — Taichung - Fab 16, Taiwan. Apply via Workday.

OMT TECHNOLOGY DEVICE and PI — Taichung - Fab 16, Taiwan. Apply via Workday.

Intern- PIE PI (Product Integration Engineering, Process Integration) — Fab 10N/X, Singapore. Apply via Workday.

Process Technician - PI Overall Process — Boise, ID - ID1. Apply via Workday.

Intern - DRAM PI — Boise, ID - Main Site. Apply via Workday.

F16 FEOL PI ENGINEER — Taichung - Fab 16, Taiwan. Apply via Workday.

Job Details: Job Description: Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans Intel's research divisions and partnerships with leading academic institutions worldwide. We are seeking an exceptional Quantum Packaging Signal/Power Integrity (SI/PI) Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for modeling and simulation of various packaging solutions from silicon redistribution layers to IC substrates within a multidisciplinary team. You'll play a crucial role in advancing Intel's silicon quantum dot technology while contributing to the development of scalable quantum systems that will revolutionize computing. Key Responsibilities - Modeling and simulation of packaging hardware including redistribution layers (e.g., interposers, RDLs), IC substrates, and silicon testchip routing - Work closely with stakeholders to meet design requirements - requirements come from both theory and hardware teams. In some pathfinding projects, you will be asked to participate in creating requirements and novel packaging hardware. - System-level modelling and simulation; end-to-end simulations to ensure designs meet system-level requirements - Deliver and disseminate design milestones to stakeholders - Communicate designs in pr

About Us: Paytm is India's leading mobile payments and financial services distribution company. Pioneer of the mobile QR payments revolution in India, Paytm builds technologies that help small businesses with payments and commerce. Paytm's mission is to serve half a billion Indians and bring them to the mainstream economy with the help of technology. About the team: Pi Agents At Pi Agents, we are creating AI agents for businesses. We are building agents that help businesses of all sizes with their day to day challenges, across the full lifecycle: Acquiring, Servicing, Retaining, Upselling, and Supporting customers. We operate like a startup inside Paytm, shipping fast with a small, senior team. About the role: This role is for the SMB Growth Agents. You will own product outcomes for growth-focused agents serving small and medium Indian businesses, taking them from capability to measurable business impact at scale. Expectations/Requirements: Own the SMB Growth Agents roadmap end to end, from problem discovery to GTM and adoption. Define and own outcome metrics: merchant activation, campaign performance, incremental revenue, retention. Design agent experiences that self-serve SMB merchants can trust and use daily: onboarding, goal setting, autonomous execution, and clear reporting. Set and enforce a very high bar for UX and UI. SMB users have low tolerance for friction; the agent experience must be simple, vernacular-friendly, and mobile-first. Work with engineering and data science on agent architecture tradeoffs: latency, cost per merchant, guardrails, evals. Run structured experimentation to prove agent-driven lift over merchant self-managed baselines. Partner with sales, ops, and support to scale from pilot cohorts to the long tail Superpowers/Skills that will help you succeed in this role: 4 to 6 years of core Product Management experience. Strong B2C product experience; experience dealing with small to medium size Indian businesses is a plus. Sets a ve