Principal Value Advisor Jobs

Principal / Senior/ Engineer, Package Characterization - APTD — Fab 10A, Singapore. Apply via Workday.

Principal Engineer/MTS – Member of Technical Staff, HIG-HBM Product System Engineering (Media Health Reliability) — Fab 10A, Singapore. Apply via Workday.

Principal Engineer/MTS – Member of Technical Staff, HIG-HBM Product System Engineering (Media Health Manufacturing) — Fab 10A, Singapore. Apply via Workday.

Principal Device Engineer, or MTS — Fab 10A, Singapore. Apply via Workday.

Principal, IO Design Engineering — Boise, ID - Main Site. Apply via Workday.

Principal IT Informatica Architect — Boise, ID - Main Site. Apply via Workday.

Principal/Staff Engineer Engineer, APTD CEM - Advanced Packaging Die Level Technology Engineering — Fab 10A, Singapore. Apply via Workday.

Principal/Staff/Senior Engineer, APTD CEM - Advanced Packaging Wafer Level Technology Engineering — Fab 10A, Singapore. Apply via Workday.

Principal Engineer, Project Design Verification Lead — Hyderabad - Phoenix Aquila, India. Apply via Workday.

Principal Engineer - Validation — Bengaluru, India. Apply via Workday.

Principal/Senior Engineer, APTD CEM - Advanced Packaging Integration Engineering — Fab 10A, Singapore. Apply via Workday.

Principal/Senior Engineer, Advanced Package Metrology-Real-Time Defect Analysis (MRDA) — Fab 10A, Singapore. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Be part of a highly skilled and challenging high-speed PHY design team working on advanced technology nodes (12nm and below). Own analog sub-blocks within the PHY and drive specification, design, simulation, reliability, and mixed-mode verification. Leverage AI-enabled tools to improve productivity and decision-making. Drive layout implementation through mask designers while ensuring compliance with process rules and DFM requirements. Participate in design reviews with internal teams and customers, explaining design choices and robustness. Collaborate with cross-functional teams across multiple global locations. Create IP EDA views including Behavioral models, Verilog-A, timing views, and abstracts. Participate in silicon bring-up, characterization, and correlation of silicon results with models and simulations. Mentor and guide junior engineers. Competitive compensation and equal opportunity workplace. Required Skills Strong analog/mixed-signal CMOS circuit design experience in deep sub-micron technologies (2nm to 28nm). Experience in High-Speed Memory Interfaces (DDR3/4/5, LPDDR5/6, GDDR5/6/7) or SerDes Interfaces (PCIe, MIPI, HDMI, USB, SATA, etc.). Full ownership experience of at least one critical PHY sub-block such as: PLL DLL CDR High-speed Receiver with Equalization Transmitter Front-End High-Speed Data Path </ul

Principal Regulatory Affairs Specialist, (Hybrid) — Portage, Michigan. Apply via Workday.

Principal Engineer, Data Platforms (Architecture & Ingestion) — NJ - Work from home. Apply via Workday.