Process Integration And Yield Enhancement Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As a Senior/ Staff NAND Design Rule Engineer in Process Integration (Storage Technology Group), your primary role is to drive and contribute to next generation 3D NAND development efforts. You will be working with several peer groups to define, execute, and coordinate effective actions to enable multiple projects to hit key achievements and timelines Responsibilities include but are not limited to the following: Define physical design rules for current and future Non-Volatile Memory (NVM) technologies from conception to full production ramp. Interact with process integration team to keep all technology developments up to date, to ensure DR's are accurate. Interact with design teams to eval

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron is a global leader in DRAM innovation, developing memory technologies that enable the next generation of computing, artificial intelligence, and data-driven applications. Within the Technology Development organization, the Process Integration team drives the development of future DRAM architectures by coordinating device, materials, and process innovations across multiple engineering fields. Team members work in a highly collaborative R&D environment to solve complex technical challenges and accelerate technology scaling. As a Process Integration Engineer Intern, you will contribute to the development of next-generation DRAM memory technologies through multi-functional collaboration involving process integration, device engineering, materials development, and process architecture. This role requires strong technical expertise, analytical problem-solving skills, and the ability to coordinate activities across multiple engineering organizations to achieve technology achievements and product objectives. Responsibilities Define technology achievements, design rules, structural requirements, and electrical specifications for next-generation DRAM technologies while supporting achievement of program targets and timelines. Collaborate with process development, simulation, process architecture, circuit design, and quality teams to ensure alignment with product and technology requirements. Develop and maintain documentation related to process integration plans, technical risks, issue resolution,

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Role Overview This internship project is designed to provide students with hands‑on learning exposure to data analytics, machine learning, and statistical modeling applied within Process Integration (PI) for advanced NAND technology development. The intern will work on a defined project focused on exploring how data‑driven approaches can support process learning, experimentation, and engineering decision‑making. Through this project, the intern will gain exposure to process, inline, and electrical datasets, and learn how analytical insights can be translated into prototypes, analyses, and documented learnings relevant to PI engineers. Key Responsibilities Build and evaluate data ‑driven models to support PI outcomes such as cycle‑time reduction, faster learning loops, and process optimization. Perform statistical analysis of split experiments (e.g., DOE‑related analysis), including data preparation, feature engineering, and model interpretation. Conduct split-DOE and conversion analytics , including datamining and statistical evaluation of split outcomes (e.g., ANOVA‑style learning). Identify opportunities to accelerate process learning</

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. 職務内容&#xff08;Job Description&#xff09; Micronのテクノロジー開発&#xff08;Technology Development&#xff09;グループに所属する DRAMプロセスインテグレーション・パスファインディングエンジニアとして、次世代DRAMテクノロジーノードに向けたモジュール開発を主導していただきます。 モジュールオーナーとして、1つまたは複数のモジュールに対する構造的および電気的要件を定義し、ユニットプロセス部門や支援チーム、ならびに他のモジュールオーナーと連携しながら、モジュールをプロセス全体に統合します。 また、多分野のエンジニアからなるチームと協働し、新しいアーキテクチャ、デバイス、技術、材料を評価することで、今後5年以上を見据えた技術開発の方向性を検証します。 主な業務内容&#xff08;Responsibilities&#xff09; 電気特性、インライン指標、ユニットプロセス、デザインルールに基づき、構造仕様を策定する 構造‐電気特性の相関に基づき、エンジニアリング仕様を満たすための実験を設計・実行・解析する モデルベースのアプローチで問題解決を行い、プロセス改善、特許、技術論文を通じて技術革新を推進する 1つまたは複数のプロセスモジュールについて、デザインルール、構造仕様、電気仕様を含めて開発・維持・改善する&#xff08;代替フロー含む&#xff09; 既存プロセスフローを最適化し、製品要件を満たす創造的な解決策を開発する JMPなどの統計解析ソフトウェアを用いて、実験の設計・実行および結果解析を行う 結果を製品側へフィードバックし、歩留まり改善に貢献する インラインデータ、欠陥データ、パラメータデータ、プローブデータを抽出・監視・解析し、 歩留まり問題の解決、性能・信頼性向上、プロセスマージン拡大、コスト削減を推進する 設計、製品技術、モデリング、歩留まり改善、電気・物理的故障解析、欠陥解析、パラメータ、品質チームと部門横断的に連携し、課題・目標・優先順位を理解する 複雑な問題を要約し、対応策を導出・説明し、チームの実行を牽引する 担当モジュール内におけるサブマイルストーンを定義する プロセスインテグレーション、プロセス開発、パイロットファブ間の円滑なコミュニケーションを維持・徹底する 製造移管に向けて、R&D活動の適時なドキュメンテーションを確実に行う 学歴・経験要件&#xff08;Education and Experience&#xff09; 修士号または博士号 &#xff08;電気工学、マイクロエレクトロニクス、物理学、材料科学&#xff09; または 学士号&#xff0b;業界経験5年以上 必要スキル・知識 半導体デバイス物理および電気特性評価に関する知識 材料科学および半導体プロセス基礎に関する知識 JMP、Python、またはその他のデータ解析&#xff0f;データエンジニアリングソフトを用いたデータ解析スキル 英語による対人・口頭・文書コミュニケーション能力 歓迎要件&#xff08;Preferred Experience&#xff09; プロセスインテグレーション、またはそれと密接に関わる職務における業界経験5年以上 DRAM製

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing . Location 1 North Coast Drive, Singapore Department Product Integration Engineering (PIE), Process Integration (PI ) Project Title Advanced Memory Process Integration Improvement Exploration and Device Reliability Study (NAND / DRAM / HBM) Project Description This internship provides a structured learning opportunity within the Process Integration Engineering team, focusing on advanced semiconductor memory manufacturing technologies, including NAND, DRAM, and HBM devices. The intern will gain exposure to reliability concepts, fail

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As a Principal/Staff Engineer, Process Integration, NTI NAND at Micron, you will have the outstanding opportunity to work on groundbreaking 3D NAND technology. This technology will develop the future of data storage solutions. This role suits those who are ambitious, enjoy solving complex problems, and want to lead innovative projects that push the boundaries of what is possible. Responsibilities Module Ownership: Lead one or more process modules related to the development and operation of 3D NAND semiconductor coordinated circuits. Specification Definition: Define structural specifications and process requirements for assigned modules. Strategic Direction: Set a clear direction and vision for the module and establish a continual improvement plan. Proactive Issue Resolution: Identify potential structure, electrical, and reliability issues early and address them with process control. Solve problems using a model-based approach. Performance Optimization: Focus on structural development, electrical performance, parametric verification, and process control. Optimize manufacturability assessments. Material Innovation: Analyze materials physically and electrically. Collaborate with process groups to select new materials for development and tran

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Position Overview: As an SPC Engineer, you are responsible for the effectiveness and efficiency of the SPC program. This includes collaborating with Process Engineering, Process Integration, RDA, and Probe departments to ensure they are adhering to the Micron Quality Standards for Statistical Process Control. Additionally, you are responsible for prioritizing inline parameters that need engineering attention, sourcing variation contributors on critical parameters, providing internal customers with SPC performance metrics, and providing CpK metrics to Micron Corporate to be shared with external customers for review. Responsibilities: Implementing SPC Business Process and Best Known Methods Understand the different types of limits used in SPC system and drives the proper use of limits throughout the engineering community Understand proper control techniques (Western Electric Rules, etc.) and enforces use for critical parameters, as needed to detect quality deviations • Works with engineering community to set appropriate goals for SPC metrics (CpK, Cp, Control limits, %OOC, etc.) on a semi-annual basis or as needed Utilize WW SPC Business Process to enforce use of BKM’s with regards to SPC Participates in WW SPC meetings to ensure the best interests of internal/external customers are considered with regards to any modifications to the WW SPC BP and/or BKM’s Regula

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Position Overview: As an SPC Engineer, you are responsible for the effectiveness and efficiency of the SPC program. This includes collaborating with Process Engineering, Process Integration, RDA, and Probe departments to ensure they are adhering to the Micron Quality Standards for Statistical Process Control. Additionally, you are responsible for prioritizing inline parameters that need engineering attention, sourcing variation contributors on critical parameters, providing internal customers with SPC performance metrics, and providing CpK metrics to Micron Corporate to be shared with external customers for review. Responsibilities: Implementing SPC Business Process and Best Known Methods Understand the different types of limits used in SPC system and drives the proper use of limits throughout the engineering community Understand proper control techniques (Western Electric Rules, etc.) and enforces use for critical parameters, as needed to detect quality deviations • Works with engineering community to set appropriate goals for SPC metrics (CpK, Cp, Control limits, %OOC, etc.) on a semi-annual basis or as needed Utilize WW SPC Business Process to enforce use of BKM’s with regards to SPC Participates in WW SPC meetings to ensure the best interests of internal/external customers are considered with regards to any modifications to the WW SPC BP and/or BKM’s Regula

What is JetZero ? Today’s aircraft contribute around 4% of global CO2 emissions, equivalent to the emissions of 200 million cars. This is only going to increase: Air travel is forecasted to double by 2050, while meaningful efficiency gains using current airplanes have hit a wall. JetZero is developing a b lended - wing body (BWB) aircraft . It uses up to 50% less fuel and will be built to accommodate zero-emission hydrogen propulsion. JetZero is the inevitable solution to sustainable air travel. The JetZero Team We are experienced aerospace professionals and engineers, excited about the future. That future will only be possible if we share our vision and what it means to people’s lives: carbon-free flight that ' i s better for both passengers and airlines around the world . JetZero is seeking an experienced Senior Aircraft Integration Engineer to support JetZero’s build and integration efforts at Mojave Air and Space Port. This position will accomplish JetZero’s integration of systems and subsystems alongside the manufacturing efforts of Scaled Composites. Aircraft Integration Engineers, including Senior level, will support development of work instructions and provide the on-site technical direction for in-process build and integration efforts in Mojave. Duties include shop coordination of weekly tasking with Scaled Composites, as well as overall management of JetZero’s onsite team execution. Other on-site duties include development of JetZero processes and procedures and coordination with JetZero’s off-site functional managers. Senior Aircraft Integration Engineer will also assist in leading the Aircraft Integration Engineering team. What You'll Do: Under the direction of JetZero’s Build Manager, support development and refinement of work instructions necessary to effectively integrate systems and subsystems into the Demonstrator airframe. In coordination with the Demonstrator Chief Engineer, provide on-site adjud

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. The Role We are seeking a thorough SOC Physical Verification & Integration Specialist to drive the physical assembly and signoff of our next-generation SOCs. In this role, you will own the physical integration strategy from the floorplan stage through to tapeout, ensuring seamless assembly of massive multi-hierarchical blocks. You will act as the critical bridge between block-level implementation, top-level integration, and final foundry signoff, ensuring that complex physical bottlenecks are resolved without compromising power, performance, or area (PPA). Key Responsibilities Top-Level Physical Integration: Drive the full-chip physical assembly of very large-scale SOCs (e.g., multi-billion transistor designs). Manage top-level floorplanning, bump planning, global power grid (PG) integration, and top-level clock/routing integration. Hierarchical Verification Methodology: Architect and deploy highly efficient, hierarchical physical verification (PV) flows. Define the boundary conditions, abstraction models, and interface rules required to assemble heavily partitioned, massive-scale designs. Signoff Execution & Debugging: Own full-chip DRC, LVS, ERC, Antenna, ESD, and Latch-up signoff using industry-standard tools (e.g., Siemens Calibre) at advanced process nodes (5nm, 3nm, or below). Cross-Functional Collaboration: Partner tightly with the Physical Design (PD

Integration meets Innovation At Celigo, we believe integration should empower — not exhaust — innovation. As a modern Integration and Automation Platform (iPaaS), we’re on a mission to simplify how companies integrate, automate, and optimize processes. Powered by game-changing technology like runtime AI and prebuilt, mission-critical integrations, Celigo is redefining how businesses connect their world. We are seeking a Senior Integrations Engineer with expertise in Enterprise System Integrations and Business Process Automation. In this role, you will design, build, and deploy scalable integration solutions and automations, as well as develop AI chatbots using various technologies across multiple domains. The Global Technology Operations team is dedicated to digitally transforming and scaling Celigo's business, enhancing productivity, and improving operational efficiency. We work closely with top talent across the company to drive both our business operations and product development. As an Integrations Engineer, you will support the business and finance teams by seamlessly connecting systems and data. Additionally, you will build automations using integrator.io and AI concepts to eliminate redundant tasks, enabling teams to focus on higher-value activities. What would you do if hired? Champion the Celigo product through transformational integrations that enable scalable business growth. Design, build, and deliver scalable data pipelines leveraging modern cloud architectures. Collaborate with business process experts to develop solutions for complex systems and data platforms that drive revenue growth. Ensure your integrations adhere to engineering best practices, emphasizing data quality, accuracy, operability, and security. Contribute to the development of AI chatbots for internal stakeholders. Build and maintain trusted relationships with technical and business teams. Manage multiple projects concurrently, including operational tasks. Serve as the owner and final

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology and amazing people. Today, we're harnessing the boundless possibilities of AI to build the next era of computing. An era in which our GPU acts as the brain of computers, robots, and self-driving cars that can understand the world. Accomplishing unprecedented goals calls for imagination, inventiveness, and exceptional talent from around the world. As a NVIDIAN, you'll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. Join our team and discover how you can build a lasting impact on the world. NVIDIA's Silicon Co-Design Group (SCG) leads the full product development lifecycle, from early architecture definition through silicon bringup to product release. The ArchDev team is the hub for silicon and system-level feature development, driving tradeoff analysis, system integration, and POR alignment across the entire organization. This is where ideas become chips, and chips become products that define the state of the art — and we're building that future with some of the most motivated engineers in the industry. We're looking for a Senior Memory Systems Engineer to own HBM and LPDDR integration in sophisticated SoCs. This role covers the full stack, including silicon, package, embedded software, testing, and product development. The engineer will resolve the toughest system-level memory challenges throughout the process, building solutions that hold up at scale. What you'll be doing: HBM & LPDDR System Integration and Bringup: Drive HBM and LPDDR system integration, bringup, characterization, and debug for next-generation SoCs — taking memory subsystems through the full arc from first silicon to production-ready at scale. Full-Stack Memory Closure: <s

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are the CMOS Device Integration Team at Micron, where we push the limits of memory technology every day. We work at the intersection of device physics, process integration, and product performance to enable the next wave of DRAM, HBM, and Compute-in-Memory innovation. If you’re excited by challenging technical problems and real-world impact, you’ll feel right at home here! In this role, you’ll serve as a technical leader shaping the future of Micron’s most advanced memory products. As a Distinguished Member of Technical Staff, you’ll drive CMOS device and module development that directly impacts array efficiency, data rates, and product scalability. Your expertise and influence will help guide technology decisions that power AI, high-performance computing, and emerging applications. Responsibilities: Develop and integrate advanced CMOS devices for next-generation DRAM, HBM, and emerging memory architectures Perform detailed electrical characterization of CMOS devices and circuits to drive performance improvements Partner with Design, TCAD, Modeling, Process, Reliability, and Layout teams to deliver integrated technology solutions Provide technical leadership, strategic recommendations, and clear presentations to guide technology direction Minimum Qualifications: Master’s degree or PhD in Electrical Engineering or equivalent practical experience 10 or more years of hands-on experience in advanced CMOS device design and/or integration 1

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, the Process Pathfinding organization develops next-generation semiconductor memory technologies and innovative device architectures. The team focuses on advancing process technologies that enable future memory products through fundamental research, process integration, and collaboration across engineering fields. This is an outstanding opportunity to contribute to innovative semiconductor development in a fast-paced, knowledge-focused environment. As a DRAM Dry Etch Process Pathfinding Intern, you will support the development of advanced plasma etch processes for emerging memory technologies. Working alongside experienced engineers and multi-functional partners, you will gain hands-on experience with dry etch equipment, semiconductor process development, materials characterization, and data-driven problem solving. This role provides exposure to advanced manufacturing environments while contributing to process solutions that improve device performance and reliability. Responsibilities Conduct experiments and fundamental research to develop innovative dry etch solutions for next-generation memory technologies. Partner with the Pathfinding team to develop and optimize dry etch processes that meet physical and electrical performance requirements. Apply analytical, statistical, and problem-solving methods to evaluate process performance, hardware capability, and process capability, and aid in

About the Team OpenAI Finance is responsible for ensuring the organization is set up for success in pursuit of its mission. The Finance Program Management Office (FinPMO) is responsible for driving and scaling cross-functional finance programs and M&A integrations. FinPMO partners closely across Accounting, Strategic Finance, Corporate Development, Equity, Procurement, Treasury, Risk, and Legal to ensure financial change through M&A and other new business models is executed in a controlled, auditable, and operationally effective way. FinPMO plays a critical role in managing M&A including financial deal diligence, finance operations, post-close integrations, reporting and controls. We help quarterback the M&A process to help ensure corporate integrations are executed cleanly, risks are managed proactively, and leadership has clear deal visibility. About the Role As a M&A Finance Integration Lead, you will own and scale OpenAI’s finance integration model. This is a highly cross-functional, transactions driven role for someone who can bring structure to ambiguity, translate deal complexity into executable workplans, and drive successful M&A outcomes across multiple teams. We’re looking for someone to be the central point of accountability to oversee finance workstreams across the full M&A lifecycle. You’ll ensure integrations are executed cleanly, financial risks are mitigated early, and our books, controls, and systems remain stable as OpenAI scales. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role you will: Define and build standardized, scalable M&A finance integration frameworks. Drive consistent execution across multiple, simultaneous M&A integrations. Ensure timely, accurate M&A diligence including historical financials, revenue, equity, tax, and procurement. Lead integration planning for deal close readiness a