Semiconductor Equipment Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Description What You’ll Do Team Leadership & Talent Development: Lead and develop global engineering and analytics teams across multiple levels. Recruit, mentor, and grow analysts, engineers, and contractors into high–performing contributors. Foster a culture of technical excellence, collaboration, and continuous improvement. Yield & Process Optimization: Collaborate with semiconductor manufacturing engineering teams to analyze inline/param/probe data to identify top yield detractors and drive continuous improvement. Data Pipeline & Automation: Extract, cleanse, and analyze datasets from SQL databases, sensor networks, and fabrication tool logs to support semiconductor manufacturing operations. Advanced Analytics & Modeling: Apply data science techniques, statistical modeling, and machine learning to troubleshoot yield issues and support defect reduction strategies. Experimentation Support: Assist process and integration engineers in running and analyzing Design of Experiments (DOE) to enhance process capabilities and margins. Visualization & Communication: Develop automated reports and dashboards using visualization tools (e.g., Dash, Plotly, streamlit) to communicate technical concepts and project outcomes

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Description As a Process Integration & Yield Enhancement Engineer of Micron, you will be responsible for driving manufacturing performance through systematic variability reduction across assembly and test. You will leverage statistical analysis and advanced data analytics to rapidly identify yield improvement opportunities and support timely, accurate production issue resolution. Through daily analysis of inline, alarm, electrical test, and experimental data, you will enable best-in-class yield, quality and reliability performance in high-volume manufacturing. Responsibilities and Tasks: Demonstrates strong understanding of yield analysis methodologies, Backend assembly and test processes, and their characteristic impacts on yield, quality and product performance. Apply knowledge of semiconductor device behavior, materials, and backend manufacturing processes to diagnose and resolve yield and reliability issues using statistical and data‑driven analysis tools. Identify and communicate process-, material-, and equipment‑related yield sensitivities to assembly and test process owners and actively support corrective actions and process optimization. Collaborate effectively with Quality, Manufacturing,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The shipment management. Coordinate and Manage the capital / tools transportation. Manage the urgent shipments and escalation cases to meet critical business requirements. Monitor carrier performance, transit times, and delivery commitments. Support transportation cost optimization initiatives. Compliance & Documentation Ensure import and export transactions comply with local and global trade regulations. Manage logistics records and documentation according to company retention requirements. Support internal and external audits related to trade compliance and logistics operations. Continuous Improvement Identify opportunities to improve logistics efficiency, quality, and cost. Support logistics automation, digitalization, and AI initiatives. Develop SOPs, work instructions, and process documentation. Participate in logistics projects and supply chain transformation programs. Required Qualifications Education Bachelor's Degree in Logistics, Supply Chain Management, International Trade, Business Administration, or related discipline. Experience 4+ years of experience in logistics, freight forwarding, customs brokerage, supply chain, or import/export operations. Experience with semiconductor, high-tech manufacturing, or global supply chain operations is preferred. Technical Skills Knowledge of Incoter

Who are we? Cohere is the leading security-first enterprise AI company. We build cutting-edge foundation AI models and end-to-end products that are designed to solve real-world business problems. We’re training and deploying frontier models for enterprises who are building AI systems. We believe that our work is instrumental to the widespread adoption of AI and we are looking for folks that want to be part of that. We obsess over what we build. Each one of us is responsible for contributing to increasing the capabilities of our models and the value they drive for our customers. Cohere is a team of researchers, engineers, designers, and more, who are all passionate about their craft. We are a global technology company headquartered in Toronto with key offices in London, New York City, San Francisco, Montreal, Paris, Berlin and Seoul. Join us! About the Role Cohere is seeking a Global Public Policy Manager to lead policy engagement on compute infrastructure, export controls, AI competitiveness, and sovereign AI strategies. Governments increasingly view AI as critical national infrastructure and are investing heavily in compute capacity, energy resources, and domestic AI ecosystems. This role will help position Cohere as a trusted partner in emerging discussions around AI infrastructure, national competitiveness, and sovereign AI deployment. Key Responsibilities Monitor and analyze developments related to AI infrastructure, data centers, energy policy, semiconductor policy, export controls, and national AI strategies. Develop policy positions on sovereign AI, compute access, digital sovereignty, and AI competitiveness. Support engagement with governments developing AI infrastructure investment programs and national AI initiatives. Collaborate with commercial, product, and corporate development teams on strategic opportunities involving public-private partnerships. Represent Cohere in policy discussions related to AI infrastructure, energy requirements, and technology c

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever! As part of the ASIC Technical Products Engineering organization, you will help drive the development of next-generation GenAI, machine learning, and advanced data analytics solutions for semiconductor engineering. In this role, you will work on intelligent systems that improve engineering productivity, strengthen technical decision-making, and unlock insights from complex ASIC pre and post silicon engineering workflows. You will collaborate with cross-functional teams across System Architecture, Logic Design, Analog/Mixed-Signal Design, Data Science and IT to prototype, build, and scale practical AI-driven solutions that improve quality, cost, cycle time, and engineering efficiency. Key Responsibilities GenAI System Development: Design, build, and improve GenAI-powered an

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron's Boise R&D site, the DRAM Technology Development organization drives innovation in next-generation memory solutions. The team develops advanced DRAM cell architectures, access devices, materials systems, and integration technologies that enable future scaling, improved performance, enhanced reliability, and manufacturing readiness. Engineers work across device, materials, process integration, modeling, design, and product engineering teams to bring groundbreaking memory technologies from concept to production. As an intern in the Advanced DRAM Device & Cell Technology team, you will contribute to the development and characterization of future DRAM cell and access device technologies through experimental studies, data analysis, and collaboration with multidisciplinary engineering teams. This position combines semiconductor device physics, materials engineering, silicon experimentation, electrical characterization, and data-driven decision making to improve cell performance, density, retention, reliability, and manufacturability. The successful candidate will collaborate with multi-functional teams to evaluate novel materials, device architectures, and integration schemes supporting future memory technology development. Responsibilities Support the evaluation of DRAM access devices, capacitors, and cell stack elements through characterization, data analysis, and assessment of new device architectures, materials systems, and integration schemes. Design and implement

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Project Title Cumulative Error Variation Reduction in Staircase and Chop Etch Processes Project Description Analyze manufacturing process and measurement data to identify sources of cumulative error variation within advanced-technology staircase and chop etch processes. Develop data-driven control strategies and process improvement recommendations to reduce variation and improve inline process stability. The project will provide exposure to dry etch processes, staircase flow integration, statistical analysis, data visualization, and the etching mechanisms relevant to semiconductor process control. Project Scope Understand the measurement methodology and process mechanisms used to define cumulative error within the staircase formation loop. Analyze process and measurement data to identify factors contributing to cumulative error variation. Apply statistical analysis and data visualization techniques to evaluate relationships between process conditions and cumulative error performance. Develop potential control strategies to reduce cumulative error variation. Recommend opportunities to improve process margins and inline stability. Learning Opportunit

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Transportation Management Coordinate air, ocean, express, and trucking transportation. Manage urgent shipments and escalation cases to meet critical business requirements. Monitor carrier performance, transit times, and delivery commitments. Support transportation cost optimization initiatives. Compliance & Documentation Ensure import and export transactions comply with local and global trade regulations. Maintain logistics records and documentation according to company retention requirements. Support internal and external audits related to trade compliance and logistics operations. Submit government-required logistics and customs reporting when necessary. Continuous Improvement Identify opportunities to improve logistics efficiency, quality, and cost. Support logistics automation, digitalization, and AI initiatives. Develop SOPs, work instructions, and process documentation. Participate in logistics projects and supply chain transformation programs. Required Qualifications Education Bachelor's Degree in Logistics, Supply Chain Management, International Trade, Business Administration, or related discipline. Experience 0~2+ years of experience in logistics, freight forwarding, customs brokerage, supply chain, or import/export operations. Experience with semiconductor, high-tech manufacturing, or global supply chain

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities: Lead design readiness activities for new DRAM products, including risk assessments, DFMEA development, validation planning, and readiness reviews Partner with cross-functional teams to identify product risks, define validation coverage, and prioritize debug activities Drive root-cause investigations of silicon findings through data analysis, experiment planning, evidence review, and corrective action development Influence product readiness decisions by connecting design intent, validation results, silicon behavior, manufacturing constraints, and customer quality expectations Mentor engineers and help improve technical practices, readiness processes, and organizational learning across DRAM programs Minimum Qualifications: Advanced degree in Electrical Engineering, Computer Engineering, Semiconductor Engineering, Applied Physics, Materials Science, or a related technical field, or equivalent industry experience Significant experience in semiconductor design, DRAM or memory technology, silicon validation, product engineering, device characterization, circuit debug, reliability, test development, or new product introduction Proven ability to analyze sophisticated technical problems using silicon data, validation results, circuit behavior, failure analysis

About Us Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Job Summary Working within the logical design team, the silicon logical design engineer is responsible for a wide range of logical design tasks. The team is responsible for delivering the Microarchitecture and RTL design to implement the chip architecture specification for Graphcore Silicon, working closely with other engineers within the Silicon team. The successful candidate will be responsible for helping the team deliver high quality micro-architecture and RTL for Graphcore chips, working within the logical design team and with the broader Silicon team to ensure we meet the company objectives for Silicon delivery. Responsibilities and Duties Integrate IP and subsystems into top-level SoC designs Develop and maintain build and configuration environments Perform synthesis, linting, CDC/RDC, and timing checks at the SoC level Support verification and physical design teams through clean interface hand-offs Debug and resolve integration-related issues across multiple hierarchies Contribute to the continuous improvement of integration flows and automation Producing high quality microarchitecture and other documentation Ensure good communication between sites to maintain consistent working practises Candidate Profile Essential skills: Logical design experience in relevant industry Experience range 4-8 years in Semiconductor Industry/Product development exposure. Be highly motivated, a self-starter, and a team player Ability to work across teams and debugging issues seen to find root caus

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Summary: As a Yield Enhancement Engineer of Micron, you will be responsible to define and communicate the issues in processing and designing which should be completed under the situation of limited wafer yield with a fast turnaround and accurate way. Through daily analysis of inline/param/probe/experiments data, achieve the best in class yield ramp as well as quality improvement. Main Responsibilities: Demonstrates thorough understanding of yield data analysis, Wafer Fabrication (Fab) processes and their common effects/signatures on yield/device. Use knowledge of semiconductor device physics, electronics and semiconductor manufacturing process to explain and resolve yield issues using various statistical/data analysis tools. Communicates the process/tool related yield toggles to the Fab process areas and support them in fixing the process/tool. Should have excellent interaction with other internal Yield Enhancement (YE) groups and work to understand their constraints. Create/participate in multi-area focus teams to solve sophisticated yield problems. Publishes a clear Pareto of yield limiters on their specific part type. </p

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Roles & responsibilities can include but are not limited to: Define the global DL4 matrices (Turnaround time, overdue matrices, detection compliance, Statistical Bin Limits (SBL) reactions etc) Ensure all sites adhere to globally aligned DL4 workflows Drive global automation and AI enhancements (YIT, Auto-contain, auto-disposition, Smart Manufacturing & Artificial Intelligence (SMAI) assisted detection) Oversee universal alignment so DL4 signal signals behave the same across sites Monitor the Assembly and Test specifications Improvements and optimization in existing DL4 systems via automation systems Spec limits (Analog values and limits, SBL Bins, Product level ESD) Test coverage/DL4 improvements (based on lessons learnt, Material review boards and Fail Mode Registers(FMR)) Network standardization (Dispositions/problems) FMR, Failure analysis, Failure analysis modelling and Defense Line Correlations Test program review and release Collaborate with cross-functional teams from Product Engineering, Media Health, Global Quality, Advanced Packaging Technology Development and Test Systems Engineering and drive projects to further enhance defense line 4 capabilities Mandatory Requirements: Strong understanding of semiconductor device physics Experience in device modelling and simulation using TCAD (Silvaco, Sentaurus, etc), as well as compact modelling. P

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Roles & responsibilities can include but are not limited to: Define the global Defense Line (DL) matrices (Turnaround time, overdue matrices, detection compliance, Statistical Bin Limits (SBL) reactions etc) Ensure all sites adhere to globally aligned DL workflows Drive global automation and AI enhancements (YIT, Auto-contain, auto-disposition, Smart Manufacturing & Artificial Intelligence (SMAI) assisted detection) Oversee universal alignment for DL signals behave the same across sites Monitor the Assembly and Test specifications Improvements and optimization in existing DL systems via automation systems Spec limits (Analog values and limits, SBL Bins, Product level ESD) Test coverage/DL improvements (based on lessons learnt, Material review boards and Fail Mode Registers(FMR)) Network standardization (Dispositions/problems) FMR, Failure analysis, Failure analysis modelling and Defense Line Correlations Test program review and release Collaborate with cross-functional teams from Product Engineering, Media Health, Global Quality, Advanced Packaging Technology Development and Test Systems Engineering and drive projects to further enhance defense line 4 capabilities Mandatory Requirements: Strong understanding of semiconductor device physics Experience in device modelling and simulation using TCAD (Silvaco, Sentaurus, etc), as well as compact modelling. <

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary The TD Electrical Device Characterization team at Micron is where deep device physics meets real product impact. We work at the groundbreaking edge of DRAM and emerging memory technologies, partnering closely across build, process, and systems teams to develop what ships next. If you enjoy turning complex measurements into insight and influence, this is a place to do your best work. In this role, you will lead electrical characterization for advanced memory devices, driving new methods from early development through production. You will combine hands-on experimentation, data-driven analysis, and technical leadership to connect device behavior to reliability, performance, and product outcomes. This position offers strong ownership, visibility, and the opportunity to mentor others while pushing technology forward. Responsibilities: Lead electrical characterization of advanced DRAM and emerging memory devices Develop and scale characterization methodologies, models, and standards Design and automate test flows, data pipelines, and analysis tools Investigate device behavior, reliability mechanisms, and root causes Collaborate across functions and present technical findings with clarity Minimum Qualifications: MS or PhD or equivalent experience in Electrical Engineering or related field Strong foundation in semiconductor device phys

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Roles & responsibilities can include but are not limited to: Define the global DL4 matrices (Turnaround time, overdue matrices, detection compliance, Statistical Bin Limits (SBL) reactions etc) Ensure all sites adhere to globally aligned DL4 workflows Drive global automation and AI enhancements (YIT, Auto-contain, auto-disposition, Smart Manufacturing & Artificial Intelligence (SMAI) assisted detection) Oversee universal alignment so DL4 signal signals behave the same across sites Monitor the Assembly and Test specifications Improvements and optimization in existing DL4 systems via automation systems Spec limits (Analog values and limits, SBL Bins, Product level ESD) Test coverage/DL4 improvements (based on lessons learnt, Material review boards and Fail Mode Registers(FMR)) Network standardization (Dispositions/problems) FMR, Failure analysis, Failure analysis modelling and Defense Line Correlations Test program review and release Collaborate with cross-functional teams from Product Engineering, Media Health, Global Quality, Advanced Packaging Technology Development and Test Systems Engineering and drive projects to further enhance defense line 4 capabilities Mandatory Requirements: Strong understanding of semiconductor device physics Experience or know-how in device modelling and simulation using TCAD (Silvaco, Sentaurus, etc), as well as compact modellin