Senior Physical Security Analyst Jobs

Senior Scientist – Physical AI for Surgical Robotics (Cambridge, MA) — Cambridge (US), Massachusetts, United States. Apply via Workday.

Senior SOC Physical Design Engineer, HBM — Richardson, TX. Apply via Workday.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a mid- to senior-level Physical Design Engineer who will contribute to the physical design of high-performance chips for industry-leading AI/ML architectures, spanning implementation from synthesis through tapeout. You will partner with front-end and physical design engineers to optimize floorplanning, timing, power, performance, and area across multiple IPs. Along the way, you will build end-to-end ASIC expertise while learning from experienced engineers across the chip development process. This role is hybrid , based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An engineer excited to work on high-performance designs for industry-leading AI/ML architectures. A collaborative problem solver who enjoys working with experienced engineers across ASIC disciplines. Grounded in logic design fundamentals and gate- and transistor-level implementation. Curious about how early architectural and RTL decisions shape physical implementation and final chip quality. What We Need A BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a relat

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a mid- to senior-level Physical Design Engineer with a strong background in static timing analysis (STA). In this role, you will help converge multi-million-gate designs on advanced process nodes and partner with cross-functional teams through final signoff and tapeout. This role is hybrid , based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A physical design engineer with 8+ years of experience in STA, timing closure, and advanced-node design implementation. Experienced with timing flows, constraints, clocking, CDC, RDC, derates, uncertainties, guardbanding, and final signoff. Skilled in writing and debugging SDC constraints, creating ECOs, developing closure strategies, and analyzing worst-case corners. A strong collaborator and communicator who can drive results across distributed, cross-functional engineering teams. What We Need Drive timing convergence across blocks, partitions, sections, and top-level designs; generate and validate timing models and publish results. Analyze timing violations, develop and propagate fixes, debug timing-flow issues, and

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an exceptional Senior-level Physical Design Engineer to drive top-level implementation of our complex AI and CPU System-on-Chip designs. You'll orchestrate cross-disciplinary collaboration, implementing sophisticated floorplans, power grids, and clock networks while ensuring design closure at the chip level. If you excel at managing the complexity of full-chip physical design and want to deliver next-generation AI hardware, we need your expertise. This role is hybrid , based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned physical design engineer who thrives on complex, full-chip implementation challenges. Expert at collaborating across disciplines, working effectively with architecture, RTL, and packaging teams. Passionate about optimizing chip-level implementations for power, performance, and area. Detail-oriented professional who drives design closure while maintaining quality and meeting aggressive schedules. What We Need 8+ years of top-level SOC physical design experience on complex, multi-million gate designs. Deep expertise in hierarchic

Senior Engineer – IC Design (Physical Design - PV/Power/EM/IR Drop Engineer) — Hyderabad. Apply via Workday.

Staff/Senior Engineer CE PYE (Physical Failure Analysis/Fault Isolation) — 2 Locations. Apply via Workday.

Staff/Senior Engineer CE PYE (Physical Failure Analysis/Fault Isolation) — 2 Locations. Apply via Workday.

Staff/Senior Engineer CE PYE (Physical Failure Analysis/Fault Isolation) — 2 Locations. Apply via Workday.

SoC Physical Design Engineer, Senior Member of Technical Staff (SMTS) — 2 Locations. Apply via Workday.

Define the physical limits of what a chip can do, then break them! NVIDIA's Silicon Co-Design Group sits at the crossroads of architecture, silicon, systems, and manufacturing, where first principles thinking translates directly into product outcomes at scale. As GPU power density and thermal limits approach physical boundaries, the gap between system architecture needs and manufacturable, testable capabilities widens with every generation, and this role exists to close it. You wouldn't be maintaining existing solutions, you'd be identifying where physical constraints will erode NVIDIA's competitive edge before anyone else sees it coming, then building the cross-domain responses that ensure the next generation leapfrogs those limits entirely. The problems here don't have known answers yet: Every generation of NVIDIA silicon pushes closer to the limits of physics. The Co-Design Architect role isn't about optimizing within known bounds; it's about redrawing those bounds entirely. If you want your work to shape what's physically possible in the world's most demanding computing products, this is where that work happens. What you'll be doing: Power, Thermal & Packaging Limits Analysis: Gather and analyze the hard constraints of packaging, power delivery, and thermal dissipation against roadmap demands, predicting when those constraints will reduce competitiveness and acting before they do. Cross-Domain Solution Development: Develop solutions that span silicon features, packaging innovation, firmware and hardware co-design, and DFX updates, ensuring future products are not only performant but testable to the highest quality and reliability standards. Packaging Technology Evaluation: Assess emerging packaging technologies for their voltage/frequency, noise, reliability, and testability implications, determining which are worth adopting an

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary: Micron Yield Improvement Failure Analysis Shift Technician that performs Electrical and Physical Failure Analysis (EFA/PFA) investigative work for defect issues identified by YE and Fab customers. Monitors recently probed material and categorizes dead die into known defect issue categories and investigates new or unknown defect issues. This position requires a strong sense of responsibility and passion, reflecting Micron’s core values: People, Innovation, Tenacity, Teamwork, and Customer Focus. Responsibilities: Performs initial data analysis on new issues, conducts failure analysis, documents findings, and summarizes investigation results—including potential root cause—into a single report for stakeholders. Efficiently operates all lab equipment in compliance with safety guidelines, with a strong understanding of equipment functionality and ability to perform basic troubleshooting. Supports Company and Department Objectives Works to support company and department objectives and vision plans Open to suggesting new ideas and participates in projects and teams in support of department and company objectives Minimum Requirements: Associates degree in Electronics, AC/DC Electronics Technology or equivalent Flexibility to work 12-hour shifts (3 on/4 off and 4 on/3 off) and be willing to move to different shifts and work overtime to support business operations. The ability to always wear lab-specific clean room garme

Who We Are Nuro believes self-driving vehicles are the most immediate and profound opportunity for AI to drive positive change in the physical world. Safer streets, more time for what matters, and easier access to the world around us, that’s why we’re building a universal autonomy platform: self-driving for all roads and all rides. Founded in 2016, Nuro is a physical AI company developing Level 4 autonomous driving technology for a wide range of vehicles, use cases, and markets. Powered by the Nuro Driver™, our universal autonomy platform enables the global mobility ecosystem to deploy autonomy at scale, from robotaxis and logistics fleets to personal vehicles. With years of real-world deployment experience and a flexible, partner-led business model, Nuro is working toward a future where millions of autonomous vehicles powered by our technology help make everyday life safer, easier, and more connected. Nuro has raised over $2B in capital from Uber, NVIDIA, Google, Softbank, Fidelity, T. Rowe Price, and other leading investors. About the Role The ability to monitor and assist our vehicles remotely plays a key role in our business strategy. As a Software Engineer, Video Streaming you will work on our in-house Teleoperations platform. You will work with a diverse team of engineers to build the core communication system as well as the cloud platform to connect vehicles and operators. This position involves broad technical understanding in networking algorithms, bandwidth estimation, rate control, computer networking, and real-time communication systems. The team is expected to deliver reliable solutions and license to 3rd party teleoperation usages. About the Work Design and implement an efficient pipeline with state-of-the-art video streaming techniques to deliver high priority real-time data stream Build an offline streaming simulation/emulation framework that can help to iterate the video streaming algorithm and predict online performance Test systems in real-world e

Who We Are Nuro believes self-driving vehicles are the most immediate and profound opportunity for AI to drive positive change in the physical world. Safer streets, more time for what matters, and easier access to the world around us, that’s why we’re building a universal autonomy platform: self-driving for all roads and all rides. Founded in 2016, Nuro is a physical AI company developing Level 4 autonomous driving technology for a wide range of vehicles, use cases, and markets. Powered by the Nuro Driver™, our universal autonomy platform enables the global mobility ecosystem to deploy autonomy at scale, from robotaxis and logistics fleets to personal vehicles. With years of real-world deployment experience and a flexible, partner-led business model, Nuro is working toward a future where millions of autonomous vehicles powered by our technology help make everyday life safer, easier, and more connected. Nuro has raised over $2B in capital from Uber, NVIDIA, Google, Softbank, Fidelity, T. Rowe Price, and other leading investors. About the Team The Devices Platform team's mandate is to lay the foundation of Nuro's onboard software for our sensor and compute platform, including device drivers, inter-device protocols and pipelines, and device runtime APIs. Sensors and compute hardware are the eyes, ears, and brains of our self-driving robots. We are creating the hardware-agnostic platform to be used by the perception and autonomy SW stack, and to realize the full potential of our sensor and compute HW in reliability, quality, and performance. The projects we work on are high impact and high visibility within Nuro. This team is also responsible for working with internal stakeholders and external suppliers to define, evaluate, integrate the next generation HW platform for Nuro's products and to build the necessary tooling to assist continuous testing and validation. About the Work Design and develop sensor and compute systems for robotics Architect and/or deploy Nuro senso

Who We Are Nuro believes self-driving vehicles are the most immediate and profound opportunity for AI to drive positive change in the physical world. Safer streets, more time for what matters, and easier access to the world around us, that’s why we’re building a universal autonomy platform: self-driving for all roads and all rides. Founded in 2016, Nuro is a physical AI company developing Level 4 autonomous driving technology for a wide range of vehicles, use cases, and markets. Powered by the Nuro Driver™, our universal autonomy platform enables the global mobility ecosystem to deploy autonomy at scale, from robotaxis and logistics fleets to personal vehicles. With years of real-world deployment experience and a flexible, partner-led business model, Nuro is working toward a future where millions of autonomous vehicles powered by our technology help make everyday life safer, easier, and more connected. Nuro has raised over $2B in capital from Uber, NVIDIA, Google, Softbank, Fidelity, T. Rowe Price, and other leading investors. About the Role Operating a vehicle remotely over cellular networks is challenging and critical. You will be responsible for ensuring that our "eyes on the road" never blink. You’ll tackle deep-stack networking challenges—from bonding multiple LTE carriers to designing custom FEC (Forward Error Correction) algorithms that out-perform standard protocols. About the Work Engineered Connectivity: Architect a network bonding framework to aggregate bandwidth across multiple cellular providers (Verizon, AT&T, T-Mobile) to ensure zero-drop connectivity. Performance Modeling: Build sophisticated ns-3-like simulations to "stress test" our stack against edge cases like tunnel entries, rural dead zones, and network congestion. Optimization: Develop and implement custom congestion control algorithms specifically tuned for high-bitrate, low-latency video streaming. Cross-Functional Leadership: Partner with Hardware and Embedded teams to optimize the netw