Staff Technical Writer Jobs

Perplexity is looking for an Infrastructure Engineer to own and improve the backend systems behind our latency-sensitive search stack. You’ll work across high-QPS Rust and Go services, distributed retrieval systems, cloud infrastructure, observability, and deployment tooling. This role combines infrastructure expertise with software engineering. You’ll take systems from design through production operation and use AI-native tools where they meaningfully improve engineering and operational workflows Responsibilities Build and operate scalable, low-latency infrastructure for search serving and retrieval. Design and improve distributed backend systems that handle high request volumes. Debug and optimize Linux systems, containers, networking, and production services. Improve reliability through observability, capacity planning, performance profiling, and incident response. Design, deploy, and operate cloud-native systems, primarily on AWS and Kubernetes. Build internal tools and automation for development, testing, debugging, and infrastructure operations. Improve CI/CD pipelines, release processes, and production rollout safety. Contribute directly to product codebases across Rust, Go, and other systems languages. Own systems end to end, from architecture and implementation to deployment and production operation. Requirements Strong experience with cloud infrastructure, distributed systems, and automation. Deep understanding of Linux internals, performance analysis, and production debugging. Experience building or operating latency-sensitive, high-throughput backend systems. Experience with containers, orchestration, observability, and infrastructure as code. Experience building or maintaining CI/CD systems and release tooling. Fluency in at least one systems language, such as Rust, Go, C++, or Java. Comfort working across infrastructure and application-level code. Strong ownership and the ability to operate effectively in a fast-moving environment. Nice To Have Experie

Who are we? Cohere is the leading security-first enterprise AI company. We build cutting-edge foundation AI models and end-to-end products that are designed to solve real-world business problems. We’re training and deploying frontier models for enterprises who are building AI systems. We believe that our work is instrumental to the widespread adoption of AI and we are looking for folks that want to be part of that. We obsess over what we build. Each one of us is responsible for contributing to increasing the capabilities of our models and the value they drive for our customers. Cohere is a team of researchers, engineers, designers, and more, who are all passionate about their craft. We are a global technology company headquartered in Toronto with key offices in London, New York City, San Francisco, Montreal, Paris, Berlin and Seoul. Join us! Please note that this is not a live role. We are grateful for your enthusiasm and interest in Cohere and encourage you to submit your resume for future consideration. Should a suitable position become available, we will review your application and reach out to discuss potential opportunities. Role Overview: Design and implement novel research ideas, ship state of the art models to production, and maintain deep connections to academia. We have one of the highest ratio of compute to engineers in the world. We do not delineate strongly between engineering and research. Everyone will contribute to writing production code and conducting research depending on individual interest and organizational needs. We have all the compute, data, and talent available for you to do your best work. Please Note: We have offices in Toronto, London, Paris, San Francisco and New York but also embrace being remote-friendly! There are no restrictions on where you can be located for this role. Key responsibilities: Design, build and scale AI systems for serving our users. Research, implement, and experiment with ideas on our supercompute and data infrastr

About Us: AI needs a new infrastructure layer. We're building it at Modal. Every era of computing brought new workloads that previous infrastructure couldn't support: mainframes, databases, and the cloud. Each time, the company that rebuilt the layer underneath defined the decade. AI is no different, except it touches everything instead of one slice, and the window to build the layer underneath it is open right now. Our customers include category-defining companies like Ramp , Cognition, DoorDash, and Suno. They rely on Modal for instant GPU access, sub-second container starts, and native storage, so it's simple to serve low-latency inference, fine-tune models, and access production-ready sandboxes at scale. We've passed $1B in annualized run rate, up 15x from a year ago. In October 2026 we raised a $750M Series D led by Accel at a $15.75B valuation. Our team includes creators of popular open-source projects (e.g., Seaborn , Luigi ), academic researchers, international olympiad medalists, and experienced engineering and product leaders with decades of experience. The Role: We are looking for strong engineers with experience and interest in designing, building, and maintaining the novel, high-performance systems that make up our serverless platform. Requirements: 5+ years of experience writing high-quality production code Experience building high-performance distributed systems at a large scale (the more battle scars, the better) Strong cloud skills Strong knowledge of low-level operating system foundations (Linux kernel, file systems, containers, etc.) Experience with performance engineering (tell us a story of when you shaved off a few milliseconds!) Ability to work in-person in our NYC or SF office. Prior experience with Rust is nice to have, but not required. Ability to participate in on-call rotation and respond to production incidents.

Member of Technical Staff (MTS), Machine Learning, SMAI — Fab 10A, Singapore. Apply via Workday.

Member of Technical Staff, AI Engineering — Boise, ID - Main Site. Apply via Workday.

Job Details: Job Description: Organization Overview: Manufacturing Development Customer Engineering (MDCE) is Intel's newest organization within Intel Foundry Technology Manufacturing (FTM). We bridge the critical gap between Technology Development (TD) and High-Volume Manufacturing (HVM), advancing technology nodes and process capability from initial product qualification to high-yield production across multiple products while enhancing technologies for our foundry customers. About This Role: Join Intel's Manufacturing Development and Customer Engineering (MDCE) team as a senior technical leader driving process innovation across Intel's most advanced semiconductor technologies in volume manufacturing. You will spearhead the development, optimization, and manufacturability of critical thin film deposition processes, ensuring seamless transitions from early development to high-volume production while meeting Intel foundry customer requirements. Your Mission: Lead thin film process excellence across CVD, ALD, PVD, epitaxy, thermal/plasma deposition, furnace, implant, anneal, and/or treatment technologies. Operating at the nexus of Technology Development and High-Volume Manufacturing, you will drive breakthrough solutions for Intel 18A, Intel 3, 12nm, and next-generation technology nodes. Key Responsibilities Process Innovation and Excellence Champion safety, quality, yield, throughput, and cost optimization across thin film deposition modules Drive defectivity reduction and uniformity improvements through systematic process enhancement Lead technical problem resolution and deliver solutions that meet aggressive technology node targets Optimize equipment performance working with internal teams and key suppliers Strateg

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron-Boise, ID, we are undergoing a historic $15 billion investment in semiconductor manufacturing; construction began in early 2023, with DRAM production slated for the second half of the decade. As a leader in the semiconductor industry, we build solutions that inspire and transform technology. With plans to invest more than $150 billion globally over the next decade in leading-edge manufacturing, we are looking for passionate people to join our Boise expansion team and contribute to the growth and innovation of the semiconductor industry. This job requisition is to seek senior technical leaders in the field of process engineering to join ID1, reporting directly to Director of DE/WP/CMP. As a member of technical staff (MTS) or Senior member of technical staff (SMTS), you will play a pivotal role in driving innovation, leading technical projects, defining the technical roadmap, and mentoring fellow engineers. Your expertise will be instrumental in developing cutting-edge DRAM process solutions to support yield ramp-up. Your contribution will have a lasting impact on the DRAM industry! Responsibilities for Process Engineering MTS/SMTS include (but not limited to): Lead the development, characterization, and optimization of Dry Etch processes for advanced DRAM structures. Collaborate cross-functionally with integration, metrology, equipment, and R&D teams to ensure process robustness and manufacturability. Define and execute

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As a key leader within High Bandwidth Memory (HBM) Product Engineering Media Health team, you will spearhead and develop a high performing team driving Media Health Manufacturing and activities for Micron’s latest HBM products, both on DRAM and Interface die and a stacked product. You will lead a portfolio of Best-In-Class Next Generation HBM Product focused on the critical KPI’s Quality, Cost, Cycle Time and Scale. This include lead the manufacturing test flow development and validation, improve the device/stacked yield with most optimized extrinsic and intrinsic reliability through in depth circuit debug, test coverage optimization and strategy innovation, test time improvement for manufacturing flow and drive the DFT (design for test) strategy to stage new ideas to improve cost, cycle time and quality. You will also collaborate with cross functional team (Fab, Product Leads, Design, Technology Development, Design, Test Solution Engineering etc) with diverse expertise to achieve both strategic and tactical objectives and stay ahead on technology and product leadership. The future of HBM are exciting and dynamics. Micron is seeking experienced individuals that find technical challenges engaging and invigorating. Responsibilities: Optimized Test Coverage: T

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As a key leader within High Bandwidth Memory (HBM) Product Engineering Media Health team, you will spearhead and develop a high performing team driving both intrinsic and extrinsic reliability test development and execution for Micron’s latest HBM products, both on DRAM and Interface die and a stacked product. Your responsibility is to drive extrinsic DPM reduction (Time 0 and Field DPM) and lead the intrinsic reliability charter, along with optimized Manufacturing Test Flow to meet critical KPI’s Quality, Cost and Cycle Time. You will be leading the team to characterize the products from reliability aspect, identify the reliability gaps, working on root cause and resolution of qual and RMA failures pertaining to defectivity and intrinsic reliability margin and drive fab process improvement driven by the qual failures. Additionally, your team will also be the key person in frontend process conversion, where you will work with Fab, TD, GQ teams to establish robust business process for process conversions to facilitate yield improvements, DPM and Cost Reduction. You will collaborate across functions within and outside of HBM to meet both strategic and tactical objectives while continually maximizing the effectiveness of the HIG HBM PE organization. The future of HBM are exciting and dynamics. Micron is s

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job / Role Summary The DMTS is a top technical authority and industry expert who defines, develops, and transfers advanced NAND dry etch processes, shapes equipment and process roadmaps, benchmarks against industry standards, and resolves the most complex yield/defectivity/integration challenges. This role carries broad technical vision, deep domain expertise , strong external engagement, and responsibility for elevating technical capability through mentorship of senior technical leaders. Main Responsibilities Act as technical expert for dry etch process, hardware, and applications in NAND technology development; provide forward-looking insight on trends, capabilities, and integration risks. Define the equipment roadmap and drive mechanism-focused hardware roadmaps with suppliers for next-generation NAND dry etch. </li

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Interested in changing the landscape of artificial intelligence workloads? Join our team where we are building next-generation, high-bandwidth memory products. In Micron's High Bandwidth Memory Architecture organization, we partner closely with customers to deliver memory solutions purpose-built for emerging AI systems and applications. As a Senior Member of Technical Staff or Member of Technical Staff, DRAM Design Engineer in the next-generation HBM Architecture team, you will drive the architecture and optimization 3D-stacked, high-performance memories. Apply your knowledge to optimize DRAM designs and architectures for maximum performance, power, and area (PPA). This role is ideal for experienced DRAM designers who will identify, architect, design, and simulate next-generation architectures and memory features in collaboration with experts in stack architecture, memory systems architecture, and SoC microarchitecture. Responsibilities: Identify and develop novel DRAM circuit architectures that anticipate next-generation AI workload requirements, to unlock improvements in bandwidth and energy efficiency. Collaborate with peers to identify the highest-leverage DRAM circuit bottlenecks and define architectural hypotheses. Validate architectural hypotheses through schematic-level circuit design, SPICE simulation, and tradeoff analysis, establishing PPA feasibility. Partner with layout designers to conduct floorplanning studies. Colla

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Role Summary The SMTS acts as a technical authority in 3D NAND cell film development, setting strategic direction and leading multi-functional initiatives to drive department-wide impact by architecting solutions, accelerating innovation adoption, influencing technical standards, and mentoring engineers to elevate technical excellence. Defines technical strategy and drives cross-org adoption; leads complex problem solving across process/hardware/device interactions with no yield trade-off; builds the SME pipeline through structured mentorship. Main Responsibilities Define technical strategy; architect solutions; influence technical standards and drive process improvements; lead advanced process development, fixing, and integration. Integrate unit processes into full cell packages and validate device/process linkages via wafer-level electricals. <

Who are we? Cohere is the leading security-first enterprise AI company. We build cutting-edge foundation AI models and end-to-end products that are designed to solve real-world business problems. We’re training and deploying frontier models for enterprises who are building AI systems. We believe that our work is instrumental to the widespread adoption of AI and we are looking for folks that want to be part of that. We obsess over what we build. Each one of us is responsible for contributing to increasing the capabilities of our models and the value they drive for our customers. Cohere is a team of researchers, engineers, designers, and more, who are all passionate about their craft. We are a global technology company headquartered in Toronto with key offices in London, New York City, San Francisco, Montreal, Paris, Berlin and Seoul. Join us! Role Overview: As a Senior Member of Technical Staff specializing in web data for pre-training, you will play a pivotal role in developing the large scale web data pipeline that underpins Cohere’s advanced language models. In this role, you will work extensively with large-scale web corpora, transforming raw, noisy internet data into high-quality training data for pretraining. You will own key components of the data pipeline, including extraction, parsing, deduplication, and filtering. You will also analyze the composition and quality of web data, study its impact on downstream model performance, and collaborate closely with the broader data and evaluation teams to iterate on the training corpus. Your work will be essential to Cohere’s mission of delivering efficient and reliable language understanding and generation capabilities, driving innovation in natural language processing. If you are passionate about transforming data into the foundation of AI systems, this role offers a unique opportunity to make a meaningful impact. Please Note: We have offices in London, Paris, Toronto, San Francisco and New York but also embrace bein

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Role Summary As a Senior Member of Technical Staff (SMTS), you are a module‑level CMP technical authority , responsible for defining CMP technical direction, leading FOAK developments, and driving cross‑functional execution across NAND nodes. As a SMTS (Senior Member of Technical Staff), you will be a part of revolutionary Next Generation NAND research & development CMP team driving Advanced NAND and CMP technology forward. The position promises ample opportunities for innovation, collaboration and testing a new dimension and scaling with Next Generation NAND. A SMTS CMP Engineer is a senior individual contributor responsible for defining, developing, and transferring advanced CMP processes for Micron NAND technologies. You will work directly with process integration and other process areas such as Wet Etch, CVD, Diffusion, Metals, Lithography & Dry Etch. You will work on state of the art and best in class CMP chambers & own the process roadmap to meet program and yield goals. Main Responsibilities Own and lead key NAND CMP process modules, translating technology challenges into executable roadmaps across current and future nodes Drive cross‑functional execution across Technology Development, Process Integration, Manufacturing, a

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Role Summary The DMTS is a recognized expert inside and outside Micron, shaping the technical vision for cell film processes with influence across top-level organizational boundaries, leading programs spanning the engineering group, driving breakthroughs, influencing industry/cross-disciplinary teams, and mentoring senior technical leaders to guide critical roadmap decisions. Owns and updates the cell film process technology roadmap; drives external collaborations and benchmarking; prepares high-impact technical deliverables (presentations/white papers/patent filings); guides investment and prioritization decisions. Main Responsibilities Serve as the CMP technical authority for NAND technology development, defining long‑term technology and equipment strategies Architect and drive next‑generation CMP process innovation, including FOAK developments, recipe architecture, and integration alignment Lead resolution of the most complex yield, defectivity, and integration challenges through deep CMP process, materials, and layout expertise Define and execute CMP hardware and supplier roadmaps, translating industry benchmarking and external insights into internal advantage Provide forward‑looking technical leadership, identifying sc