System Verification Co Design Engineer Jobs

SCG sits at the crossroads of design, architecture, marketing, and productization—owning the journey from the architecture stage through final product definition across Gaming, Datacenter, Automotive, and Embedded markets. As a System Verification CoDesign Engineer, you will work on system-level speed features, develop the verification collaterals and automation infrastructure to characterize and validate them, and lead debug of the complex silicon issues that stand between a program and on-time shipment. This is a hands-on role for an engineer who combines deep technical craft with the drive to compress cycle time using modern tooling—including AI—without losing rigor. What You’ll Be Doing: Collaborate cross-functionally with system architects, hardware, firmware/software, process/reliability, and operations teams to co-design system-level speed features and deliver industry-defining products. Understand system level behavior and speed reliability margins, bounding box constraints and identify solutions that optimize margins . Translate hardware features and architectural requirements into verification techniques that achieve full coverage across testing flows. Perform closed loop validation by correlat ing silicon behavior against timing simulation and design expectations; provide actionable feedback to improve future designs. Define, prototype, and refine pre- and post-silicon bring-up flows to ensure

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role You will build the low-level device runtime that turns compiled programs into efficient, functional and performant execution on OpenAI’s custom AI accelerator. This software will schedule kernel launches, manage device memory and address spaces, coordinate synchronization, and expose reliable abstractions to higher-level runtimes and frameworks. You will work at the boundary of software and hardware, partnering with compiler, kernel, architecture, verification, and silicon teams to define interfaces and validate behavior. You will also use and improve event-based, cycle-accurate simulation to develop runtime capabilities before silicon is available, diagnose performance and correctness issues, and guide hardware-software co-design. In this role, you will: Design and implement the low-level device runtime for OpenAI custom silicon. Build kernel-launch scheduling, command submission, queueing, dependency tracking, and completion handling. Manage device memory spaces, allocation, virtual-to-physical mappings, data movement, and lifetime across concurrent workloads. Implement synchronization primitives, events, barriers, streams, and ordering guarantees that are correct and efficient. Define clean interfaces between the runtime, drivers, firmware, compiler-generated code, kernels, and higher-level execution systems. Use event-based, cycle-accurate simulators to develop, validate, debug, and performance-tune runtime behavior before and after silicon availability. Di

About the Team: OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale. In this role you will: Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality. Define verification plans based on architecture and microarchitecture specs. Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies. Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness. Drive bug triage, root cause analysis, and work closely with design teams on resolution. Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments. You might thrive in this role if you have: BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification. Proven success verifying complex IP or SoC designs in industry-standard flows Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi). Strong knowledge

Senior DevSecOps Software Engineer Company: The Boeing Company The Boeing Company has an exciting opportunity for a Senior DevSecOps Software Engineer to support the Protected Tactical Enterprise Service (PTES) team in Colorado Springs, CO. As a DevSecOps Engineer on the Protected Tactical Enterprise Service (PTES) team, you will be responsible for integrating security practices within the development and operations lifecycle of tactical enterprise systems. You will collaborate closely with software developers, security teams, and infrastructure engineers to design, implement, and maintain secure, automated CI/CD pipelines, ensuring the delivery of resilient and compliant services in protected operational environments. Position Responsibilities: Leads the design, development, analyses, and maintenance of software systems that meet industry, customer and internal quality, safety, security and certification standards Partners with appropriate stakeholders to inform system definition and reviews translation of system-level requirements into software requirements and models that meet customer, operational and performance requirements and have clear traceability to design, code and test artifacts Reviews completion of software system-level analyses to identify risk, issues and opportunities; leads integration and deployment of mitigation actions throughout the software lifecycle. Leads code reviews to ensure alignment to requirements and standard Leads monitoring and reviewing test completion, verification processes and issue resolution for software systems Leads development of user documentation and training to educate end users about usage of software products Leads review of pr

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for a software engineer to help build the design methodology, software abstractions, and infrastructure that enable a small silicon team to develop complex chips rapidly and with high confidence. You will turn evolving architecture and design needs into reusable tools and workflows that improve iteration speed, quality, and then apply those tools to help construct world-class silicon. You’ll work closely across architecture, design, verification, performance modeling, and systems software. This role is well suited for an engineer who enjoys building high quality software and is motivated by the challenge of improving velocity and quality of the silicon development process. In this role, you will: Develop and scale design methodologies for rapid first-party chip development and apply them to construct complex custom chips Create abstractions that allow hardware structures, configurations, experiments, and results to be represented consistently across tools. Automate high-value engineering workflows and improve their reproducibility, observability, testability, and ease of use. Partner with architects, RTL designers, verification engineers, compiler engineers, and systems software engineers to gather requirements and then implement solutions. Use methodology and tooling to identify design risks early, accelerate iteration, and improve confidence in performance and implementation tradeoffs. Contribute across multiple aspects of software and hardware

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale. This is a senior, hands-on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure, physical design convergence, bring-up, and production readiness. You will plan and oversee the work of junior engineers and help drive and develop productive engineering relationships with external partners and help manage partner execution. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic as well as off-chip protocol bridges and interfaces. Drive third party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and de

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role You will develop and evolve the tooling ecosystem that hardware engineers rely on every day — from hardware compilers and IR transformations to simulation, debugging, and automation infrastructure. The work spans software engineering, compiler concepts, and practical hardware workflows, with direct impact on how quickly and effectively we design next-generation AI systems. You’ll collaborate closely with architects, RTL designers, and verification engineers to translate real engineering friction into durable, scalable tooling solutions. In this role you will: Build and improve the software tooling that makes hardware teams faster: compilation, IR transforms, RTL generation, simulation, debug, and automation. Extend and integrate hardware compiler stacks (frontends, IR passes, lowering, scheduling, codegen to Verilog/SystemVerilog) and connect them to real design workflows. Improve developer experience and reliability: reproducible builds, better error messages, faster iteration loops, and dependable CI and regression infrastructure. Work closely with designers and verification engineers to turn real pain points into durable tools. Dive into RTL when needed: read and reason about Verilog/SystemVerilog to debug issues, validate tool output, and improve debuggability. Be willing to go all the way down the stack when necessary, including gate-level views, synthesis results, and implementation artifacts. Help enable PPA optimization loops by building analysis and au

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As a NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. Silicon Co-Design Group (SCG) is a wide-ranging, multi-functional, integral team at NVIDIA. We sit at the crossroads of design, architecture, marketing, operations, and productization. Our contributions span from the arch stage and extend to defining final products. We architect innovative solutions for Datacenter, Server, Gaming, Robotics, Automotive, and Embedded markets. We are fast-paced, dynamic, share a sense of humor, and collaborate extensively to push the boundaries of what is possible. We do all of this with an eye on making groundbreaking, impactful market disruptions! We are seeking an experienced Senior Manager to lead Product Co-Design and Verification in areas of Speed, Reliability and Power Compliance. You will oversee speed/timing/reliability system design, Simulation-to-Silicon power/speed verification, features for product compliance and test chip development crating future product roadmaps. The ideal candidate will have deep technical expertise in semiconductor/VLSI design and a background in translating product requirements into design and vice versa. This is a highly visible, multi-functional role to produce outstanding products that ship at SOL and meet the high NVIDIA quality we demand and customers expect. <p

Remote Web Developer (Equity Partner 10%) Role Type: Founding Web Developer (Equity-Based) Location: Remote Experience: Freshers Welcome (Strong builders preferred) Compensation: 10% Equity (Vesting-Based) Cash Compensation: None initially About the Startup We are building two high-impact digital platforms: 1️ Solar Fintech Platform A fractional ownership platform where: • Users buy micro-shares (e.g., 100 units) of solar panels. • Once fully funded, solar panels are deployed to corporates. • Energy generation produces returns distributed proportionally to shareholders. Core Components: • Investor dashboard • Payment integration • Solar performance analytics • Admin & corporate PPA tracking 2️ Carpooling Platform (Similar to Mitfahrgelegenheit) A ride-sharing website connecting drivers and passengers traveling between cities. Core Components: • Driver ride listing system • Seat booking & payment • Route matching • Ratings & verification • Real-time notifications Role Overview As a Founding Web Developer, you will architect, build, and deploy both platforms from scratch. You are not just a coder you are a technical co-builder. Key Responsibilities Product Development • Develop full-stack web applications (frontend + backend) • Build scalable database architecture • Implement secure payment gateway integrations • Develop admin dashboards • Deploy MVP and iterate rapidly Solar Fintech Specific • Micro-share allocation logic • Wallet & transaction history system • Solar data API integration • ROI calculation engine • Investor performance dashboard Carpooling Platform Specific • Ride-matching algorithm • Location-based search • Booking & seat allocation system • Driver/passenger profile system Infrastructure • Cloud deployment (AWS / GCP / Azure) • CI/CD pipelines • Basic cybersecurity implementation • API architecture Skills Required • React / Next.js / Vue (Frontend) • Node.js / Django / Laravel (Backend) • SQL / NoSQL databases • Payment gateway integration exper

Work Flexibility: Onsite This role will be based in one of our Cork sites. Perform testing on medical device products and components using automated, semi-automated and manual methods. Follow test request protocols and report through mainly written but also verbally on the results of the tests. Evaluate variable data and understand and articulate attributes of product and component performance. Throughout the placement, you will be an integral part of Stryker’s 2026 Cooperative cohort. Tasks and responsibilities may include: Together, with your Stryker team leader and college supervisor, identify a process improvement project along with project objectives, scope, success factors, milestones and evaluation metrics Provide support to Research & Development, Advanced Operations and Global Quality Operations on the development and verification testing of new and existing products Develop and coordinate inspection and testing procedures for prototypes, components and products Formulate test guidelines and procedures and recommend revisions of specifications where necessary Set up and perform routine to non-routine experiments of moderate scope which comply with FDA requirements and appropriate engineering standards Extract and process test data/findings into both formal written and verbal reports which comply with FDA requirements and appropriate engineering standards Assist in designing, installing and maintaining process sampling systems, procedures, statistical techniques, testing mechanisms, equipment and fixtures Comply with documentation procedures and maintain test laboratory housekeeping standards to the highest level Coordinate with facilities and

GitLab is the intelligent orchestration platform for DevSecOps. GitLab enables organizations to increase developer productivity, improve operational efficiency, reduce security and compliance risk, and accelerate digital transformation. More than 50 million registered users and more than 50% of the Fortune 100* trust GitLab to ship better, more secure software faster. The same principles built into our products are reflected in how our team works: we embrace AI as a core productivity multiplier, with all team members expected to incorporate AI into their daily workflows to drive efficiency, innovation, and impact. GitLab is where careers accelerate, innovation flourishes, and every voice is valued. Our high-performance culture is driven by our values and continuous knowledge exchange, enabling our team members to reach their full potential while collaborating with industry leaders to solve complex problems. Co-create the future with us as we build technology that transforms how the world develops software. * Fortune 500® is a registered trademark of Fortune Media IP Limited, used under license. Claim based on GitLab data. Fortune 100 refers to the top 20% ranked companies in the 2025 Fortune 500 list, published in June 2025. Fortune and Fortune Media IP Limited are not affiliated with, and do not endorse products or services of GitLab. An overview of this role As a Senior Backend Engineer at GitLab, you will help build the core capabilities of our dedicated software supply chain security Add-On. This commercial offering helps organizations control what software enters their builds, verify the integrity of what they ship, and identify malicious packages before they reach production. You will work across a set of connected backend systems that support package policy enforcement, artifact signing and verification, provenance attestation, and malicious package intelligence. This is a founding role on a small team with a high level of responsibility. The engineering

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a highly skilled and motivated Senior Design Verification Engineer to join our team. In this role, you will be responsible for the end-to-end verification of our IOMMU (Input/Output Memory Management Unit) IP. You will play a critical role in ensuring the functional correctness and performance of the design, taking ownership of the verification process right from the initial specification understanding down to final coverage closure. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You have hands-on experience in ASIC or SoC verification using SystemVerilog and UVM. You enjoy debugging complex design and verification issues and working closely with cross-functional teams. You’re comfortable building verification environments from scratch and driving coverage closure. You have familiarity with standard bus protocols and modern verification tools. What We Need Experience owning block or subsystem-level verification from test planning to sign-off. Strong understanding of constrained-random verification, coverage analysis, and regression debugging. Familiarity with proto

At NVIDIA, we push the boundaries of computing innovation. Our ASIC Verification Engineers focus on developing the world’s top SoCs and GPUs. Joining us as a Senior ASIC Verification Engineer - GPU means working on modern technology powering consumer graphics and AI applications. This position is ideal for those passionate about technology and eager to impact computing’s future. What you'll be doing: As a key member of our ASIC Verification team, you will verify the design and implementation of the industry's leading GPUs. You will be responsible for verifying the ASIC build, architecture, golden models, and micro-architecture using advanced verification methodologies such as UVM or equivalent. Understand the design and implementation of your unit/cluster/chip, define the verification scope, develop the verification infrastructure, and verify the correctness of the design. Collaborate with architects, designers, and pre- and post-silicon verification teams to accomplish your task. What we need to see: Bachelor's Degree in EE, CS, or CE or equivalent experience. 5&#43; years of relevant experience. Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies. Experience with design and verification tools (VCS or equivalent simulation tools, debug tools like Verdi, Indago, GDB). Expertise in System Verilog or similar HVL. Strong debugging and analytical skills. Perl and C/C&#43;&#43; programming language experience desirable. Strong communication skills and the ability & desire to work as a great teammate are huge pluses. Experience in crafting test bench environments for unit and system level verification. #LI-Hybrid Your base salary will be det

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Our Tensix team is building custom AI compute cores, RISC-V CPUs, and chiplet-based architectures for datacenter, edge, and automotive AI. Design Verification Engineers on this team validate compute IP and subsystems and build scalable DV infrastructure to keep verification fast, automated, and production-grade. This role is hybrid, based out of Toronto, ON, Austin, TX or Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experienced in modern verification methodologies with strong SystemVerilog skills and exposure to structured testbench development. Comfortable working from block-level to system-level verification and reasoning about microarchitecture behavior from specs and waveforms. Proficient in Linux environments with Python, or Bash scripting for automate builds, parse logs, manage CI pipelines. Skilled in coverage-driven verification and confident debugging across RTL, testbench, and workload scenarios. Motivated by AI hardware and eager to learn verification strategies for new architectures and domains. What We Need Contribute to verification of Tensix IP and subsystems from early planning through tape-out, owning cov

We anticipate the application window for this opening will close on - 10 Oct 2026 Careers that change lives start here. Medtronic is a global leader in healthcare technology with a Mission to alleviate pain, restore health, and extend life. Our 95,000 employees work across more than 150 countries to put patients first — developing innovative medical technologies that improve the lives of 72&#43; million patients each year. Your unique talents will help shape the future of healthcare while building a career grounded in purpose, growth, and impact. A Day in the Life The Neuromodulation Research & Development organization develops therapies and technologies that address chronic pain and other neurological conditions. Within the Interventional Pain portfolio, teams focus on minimally invasive therapies used to treat musculoskeletal pathologies, including vertebral compression fractures, nerve pain, metastatic bone tumors, and benign bone tumors. This role supports the development of system-level verification and validation strategies for new products and enhancements across mechanical, electrical, and software components. This position is based in Santa Clara, California, and follows an onsite work model. No travel is required for this role. As a Research & Development Test Engineer, you will lead and execute verification and validation activities that support the development of interventional pain therapies and associated medical device systems. You will collaborate with cross-functional partners to define test strategies, evaluate product performance, manage technical risks, and generate evidence needed to support product development and regulatory requirements. Primary Responsibiliti