Test Automation Handler Engineer Jobs

About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you’ll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Join forces with us on our mission to build a better IT industry. We are currently looking for a highly skilled Embedded Software Engineer to our team in Stockholm or Malmö, Sweden. Please note that applicants must live in Sweden and hold a valid work permit at the time of application to be considered for this role. Responsibilities: Design, implement, and debug embedded firmware for 802.15.4 Thread-based devices (border routers, RCPs, sleepy/end devices) running on an RTOS and embedded Linux Integrate and maintain the OpenThread stack and Matter commissioning/data-model layers across the product line Work closely with hardware engineers on SoC/MCU bring-up and debug radio timing, RF, and low-power issues at the driver level Implement and troubleshoot Thread border routing, SRP, and network commissioning/joining flows, including bridging to Wi-Fi/Ethernet backbones Diagnose firmware-level issues using JTAG/SWD debuggers, logic analyzers, and protocol sniffers/packet captures Write and maintain unit and integration tests; participate in code review Contribute to OTA update pipelines and manufacturing/production test tooling Requirements: Strong proficiency in C++ (99 % code base) and C for embedded systems Hands-on experience with an RTOS (FreeRTOS, Zephyr, or similar) Solid MCU debugging skills Solid networking fundamentals, incl

Here's a summary of the role: You're a hands-on engineer who enjoys solving complex data challenges at scale. You'll join the Data Hub team, building the shared data platform that supports reporting, analytics, AI, and Data Science initiatives across Diligent. Working with Python, SQL, AWS, and cloud-native technologies, you'll help process, organize, and enrich large volumes of data while developing scalable services and modern data solutions. You'll collaborate closely with Product Managers, Engineering Managers, and fellow engineers to deliver high-quality features, improve platform capabilities, and shape the future of our data ecosystem. If you enjoy ownership, solving challenging problems, experimenting with new technologies, and working in a collaborative environment, you'll fit right in. Here's a breakdown of what you'll do (not all of it, just the important stuff): Design, develop, review, and test features and user stories following Agile development practices Contribute to core platform development and integration projects across multiple systems Participate in shaping the future architecture of the product , including designing scalable backend services and prototypes Collaborate with Product Owners and Engineering Managers to analyze, refine, and document technical requirements Build and maintain cloud-native solutions and microservices-based applications Leverage AI-assisted development tools , code assistants, and modern engineering workflows to improve delivery efficiency Support the creation and maintenance of high-quality operational and technical documentation Continuously identify opportunities to improve engineering processes, quality, and team effectiveness These are the essentials you'll need to get an interview: 2+ years of experience in a hands-on software development role within a commercial software environment Strong programming experi

ABOUT BASETEN Baseten powers mission-critical inference for the world's most dynamic AI companies, like Cursor, Notion, OpenEvidence, Abridge, Clay, Gamma, and Writer. By uniting applied AI research, flexible infrastructure, and seamless developer tooling, we enable companies operating at the frontier of AI to bring cutting-edge models into production. We're growing quickly and recently raised our $1.5B Series F , led by Altimeter Capital, Conviction Partners, and Spark Capital. Join us and help build the platform engineers turn to ship AI products. THE ROLE We are bringing our people systems in-house on Workday, and we are hiring our first dedicated Workday Analyst to make it excellent. You will join while the implementation is underway, ramp alongside our deployment partner, and own the tenant from go-live onward. This is a hands-on configuration role: you will build business processes, manage security, load data, and test releases yourself, and you will teach others on the People team to do the same as we grow. If you want to shape a Workday environment from its first day in production instead of inheriting years of someone else's decisions, this is that rare opening. RESPONSIBILITIES Own day-to-day Workday configuration: business processes, security groups and roles, custom reports, calculated fields, and tenant settings Build and run EIB loads for data changes, mass updates, and audits Own the twice-yearly Workday release cycle: evaluate new features, regression-test, and roll out changes safely Shadow the implementation build, then take over tenant ownership at go-live Monitor integrations and triage issues with our IT team and vendors Support payroll configuration in partnership with our Accounting team and payroll services provider Field and resolve system requests from employees, managers, and the People team Mentor teammates so Workday administration becomes a team capability, not a single point of failure REQUIREMENTS 6+ years administering a live Workday

About the Team The Technology Vertical team builds within Core Products. The team’s mission is to transform every major function in a technology company with AI to drive higher economic output, while people remain owners of the outcomes: setting intent, applying judgment and craft, directing iteration, and owning the result. About the Role As a Product Manager on the Technology Vertical team, you will shape how knowledge workers use AI in their daily work. You’ll craft enterprise products at the intersection of novel research capabilities and genuine enterprise needs, driving the full feedback loop from research, to product, to OpenAI’s own enterprise functions, to the broader Technology Vertical. This role is based in San Francisco, CA. We use a hybrid work model of three days in the office per week and offer relocation assistance to new employees. In this role, you will: Own the product roadmap for a line of business within tech verticals, using OpenAI’s organization to test, refine, and scale new workflows. Develop the ecosystem strategy across technology partners in your line of business You might thrive in this role if you: Have built enterprise products for non-developer knowledge workers and understand the needs of both individual contributors and organizational buyers. Can turn complex workflows, integrations, and permission requirements into clear product decisions. Are comfortable developing a strategy while working closely with engineers, customers, and cross-functional partners to ship and learn. Bring strong judgment about which vertical-specific needs should become reusable capabilities across a broader product. About OpenAI OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and

Zscaler (NASDAQ: ZS) accelerates digital transformation so customers can be more agile, efficient, resilient, and secure. The Zscaler Zero Trust Exchange platform protects thousands of customers from cyberattacks and data loss by securely connecting users, devices, and applications in any location. Distributed across 200+ public data centers globally and thousands of private sites at the edge, the SASE-based Zero Trust Exchange is the world’s largest in-line cloud security platform. We believe the future of work is Human + AI and are building an AI-native enterprise where human potential is amplified by machine intelligence to solve the world’s hardest security challenges. Driven by deep customer obsession, we are committed to the mission, outcome, and to each other. We bring these commitments to life through three core behaviors: ownership and collaboration, trust through outcomes and impact, and a challenge culture with ongoing feedback. Ready to make an impact at the company pioneering security transformation in the AI era? Join us at Zscaler. We are looking for a Principal Specialist Sales Engineer for Data Security serving our customers in the Majors segment. This reports directly to the Director, Specialist Sales Engineers, Data Security. In this role you’ll partner closely with sales teams to shape and win strategic opportunities. You will translate complex customer requirements into compelling solutions, lead hands-on evaluations, and guide prospects to successful outcomes. What You’ll Do Create and deliver technical product presentations to prospective customers. Gather customer technical requirements to ensure proposed solutions align to goals and needs. Lead product evaluations and custom product configurations. Design evaluation test plans with customers and guide the process to successful outcomes. Who You Are (Success Profile) You act like an owner — biased for action, accountable, and able to flex from strategy to hands-on execution. You ar

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The TD Electrical Device Characterization team pushes the boundaries of Micron’s memory technology. We explore device behavior, uncover insights through data, and collaborate across engineering teams to enable next-generation products. We are a hands-on team that values curiosity, precision, technical rigor, and collaboration. In this role, you will drive electrical characterization for advanced memory technologies and partner with device, process, and product teams to turn measurements into actionable technical insights. Your work will help guide technology development and shape the performance and reliability of future NAND, DRAM, and emerging memory products. Responsibilities: Lead electrical characterization for advanced memory devices Develop measurement methods, algorithms, and scalable characterization standards Automate data pipelines and analysis using Python, JSL, C/C&#43;&#43;, and dashboard tools Architect test setups and manage wafer probe and ATE test flows Investigate device behavior, identify root causes, and communicate technical findings Minimum Qualifications: <span style="color:#6

Job Details: Job Description: Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans Intel's research divisions and partnerships with leading academic institutions worldwide. We are seeking an exceptional Quantum Packaging Modeling Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for thermal modeling and simulation of various packaging solutions from silicon redistribution layers to IC substrates within a multidisciplinary team. You'll play a crucial role in advancing Intel's silicon quantum dot technology while contributing to the development of scalable quantum systems that will revolutionize computing. Key Responsibilities - Thermal modeling and simulation of packaging hardware to understand how heat flows from silicon test chips through various heat spreader hardware - Manage the overall integration of the packaging hardware and enable co-design between relevant stakeholders - Work closely with mechanical designers to define heat spreaders for optimal performance - Deliver and disseminate design milestones to stakeholders - Communicate designs in presentations and relevant documentation - Stay current with the latest developments in packaging technology and design techniques by attending conferences and rea

Job Details: Job Description: The Role and Impact: We are seeking a Manufacturing Quality and Reliability Engineer to join the Foundry QnR team at our Penang site, supporting Intel's advanced packaging programs (EMIB, Foveros). This role spans silicon processing and wafer-level assembly (WLA) flows, and key interfaces with packaging substrates and 2.5D EMIB technology. You will help ensure that products and processes meet rigorous quality and reliability standards from wafer fabrication through packaging and assembly. The position directly influences manufacturing performance, yield, reliability, and customer satisfaction by driving robust quality control, disciplined excursion management, and continuous process improvement. You will also have the opportunity to represent Quality and Reliability in development forums, Silicon and Advanced Packaging factory operations, and Substrate suppliers. Key Responsibilities Apply Advanced Packaging expertise to assess inline process health, excursion impact, yield risk, defect mechanisms, and downstream packaging implications. Collaborate with cross-functional teams to drive effective root cause analysis, systemic corrective and prevention actions using 8D and related problem-solving methodologies. Partner with fab manufacturing, substrates assembly, test, process engineering, and quality teams to strengthen early excursion detection, process controls, in-line screens, and outgoing quality. Drive quality control improvements devising incoming/ outgoing quality controls, using statistical process control, defect pareto analysis, control plans, audit learnings, and excursion prevention indicators across fab, substrate manufacturing, and assembly manufacturing steps. Support manufacturing excursion management, including MRB facilitation, cont

NVIDIA’s Silicon Co-Design Group sits at the crossroads of architecture, silicon, systems, and manufacturing, where first-principles thinking and engineering judgment at the highest level translate directly into product outcomes at scale. We are looking for a Principal Performance and Manufacturing Architect who has built the models, defined the specs, and seen them validated through silicon. You have owned the connection between design intent and manufacturing reality, not as a reviewer or a contributor, but as the person who set the methodology and proved it worked. You turn ambiguous physical phenomena into quantified, defensible margin terms. You do not wait for data to confirm your hypothesis; you design the experiment that gets it. You improve how the organization ships products after every program. The exceptional hire also uses AI deliberately — with proven workflow impact and the judgment to know where it compresses real work and where it introduces risk. What you'll be doing: Own the physics, from mechanism to margin. Build first-principles models connecting AVF, defect mechanisms, and DVFS transients to field FIT, system-level yield, and DPPM vs. coverage — calibrated per node and population shift — so every margin term in the V/F curve and P-state table is named, sourced, and defensible. Set the screen that resolves escapes. Specify ATE and SLT voltage, frequency, and timing conditions that capture worst-case transient VF windows — making it unambiguous whether a marginal defect or timing violation is detected or escapes at every manufacturing stage. Make the POR the authoritative source. Author the methodology document for each program and drive alignment across build, product definition, reliability, and test engineering — so every team is making decisions from the same model. Prove the model before produc

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are a world - class autonomous driving hardware and software development team. We have the best platform and have maintained a leading position in the field of artificial intelligence. Next, we will continue to deepen our efforts in the autonomous driving field and strive to bring sustained growth to our customers. We're looking for a Senior Software Triage Engineer with strong technical ability to deeply understand architectures and strong scripting experience to automate and Triage methodology, and the leadership to encourage our engineering team. As a key member of our automotive group, you'll be working on the real time challenges outstanding to the automotive industry and our automotive products. This is a key role to support AV software agile iteration & development for the release of clients, together working with the engineering teams, understanding the AV stack deeply and providing data-based judgement and delivering high-quality AV software to end customer. What you’ll be doing: Work with Product, Engineering, Model/SW Devs, In-car testing, Fleet teams on test request and triage planning, do live triage with accurate analysis and debugging steps, present top issues by end of day. Deep understand

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. System Integration sits at the intersection of all of them. It is the layer where every architecture, design, software, and manufacturing decision meets reality. When something breaks late in a program, it usually breaks here first. We are hiring a Senior Manager to lead this team in the US and partner closely with teams globally. Your work will sit on the critical path of every NVIDIA silicon program, and the bar you set for system integration is the bar we ship to! The two hardest, highest-leverage problems in this seat: Find critical silicon issues earlier — often before software is production-ready. Left-shifting post-silicon coverage is the highest-value thing System Integration can do. Standing up wide-area testing as a repeatable capability is a core part of the role. Keep programs on milestone when upstream dependencies slip. Validation plans collide with reality every program! The team needs new strategies, not just contingency plans, to keep moving when software, firmware, or methodology slip. You will design and run those strategies. What you’ll be doing: Plan and execute post-silicon feature integration, PVT validation, and wide-area testing across NVIDIA’s GPU, SoC, and CPU programs. Build wide-area and in-system test as a repeatable capability that shifts post-silicon coverage left, so issues surface before we are production-ready. Lead resolution of the most complex system-level issues, RMAs, and HW/SW interaction problems with creative workarounds and focused lab experimentation. Deve

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As a NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. Silicon Co-Design Group (SCG) is a wide-ranging, multi-functional, integral team at NVIDIA. We sit at the crossroads of design, architecture, marketing, operations, and productization. Our contributions span from the arch stage and extend to defining final products. We architect innovative solutions for Datacenter, Server, Gaming, Robotics, Automotive, and Embedded markets. We are fast-paced, dynamic, share a sense of humor, and collaborate extensively to push the boundaries of what is possible. We do all of this with an eye on making groundbreaking, impactful market disruptions! We are seeking an experienced Senior Manager to lead Product Co-Design and Verification in areas of Speed, Reliability and Power Compliance. You will oversee speed/timing/reliability system design, Simulation-to-Silicon power/speed verification, features for product compliance and test chip development crating future product roadmaps. The ideal candidate will have deep technical expertise in semiconductor/VLSI design and a background in translating product requirements into design and vice versa. This is a highly visible, multi-functional role to produce outstanding products that ship at SOL and meet the high NVIDIA quality we demand and customers expect. <p

NVIDIA's accelerated computing platforms move data at speeds that push the limits of what silicon and physics allow. Whether a high-speed interface trains reliably, maintains accurate margins, and survives every platform topology it will ever see is a question we answer ourselves. This role does that work. The Silicon Co-Design Group leads the boundary between what was designed and what was built. When a GPU, CPU, or SoC ships with interfaces that work at scale, this team is the reason. Most engineers debug within a layer. You will own the full stack. When an interface fails to train, the link margin is unexpectedly tight, or a customer reports a critical silicon issue, you trace the problem through protocol behavior, signal integrity, firmware, platform topology, and silicon marginalities. You then confirm that the fix works. Your methodology shapes how NVIDIA validates high-speed interfaces across generations. Your decisions affect yield, production ramp, and field quality. This is not a coordination role. The engineers who do it well hold protocol depth and system breadth simultaneously, never lose the thread across hardware, firmware, and software, and have the judgment to know when to go deeper and when to act. They are rare. Should that describe you, read on. What you'll be doing: Own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other HSIO interfaces across NVIDIA GPUs, CPUs, and SoCs from first power-on through production readiness. Close the hardest failures. Drive root cause across protocol behavior, signal integrity, firmware and driver interactions, platform topology, and silicon marginalities and own every fix through to confirmation. Define validation strategy. Set test coverage, debug priorities, margining methodology, and stress criteria f

NVIDIA has been redefining computer graphics, desktop gaming, and enhanced computing capabilities for more than 25 years. Today, we are tapping into the unlimited potential of AI to define the next era of computing. As a NVIDIAN, you will work on problems that sit at the boundary of architecture, silicon, firmware, software, and production, where strong judgment matters as much as technical depth. We're the Silicon Design for Productization (DFP) Team, within the broader Silicon Co-Design Group, and we turn power and thermal design into executable productization methodology. Power and thermal are among the most complicated problems we work on at NVIDIA because they sit at the intersection of architecture, workload behavior, silicon variation, firmware policy, platform constraints, and product goals. Small decisions here have an outsized impact on performance, efficiency, reliability, bring-up speed, and ultimately what the product can deliver in the field. We define how features move from concepts to bring-up, characterization, validation, and release. In this role, you will help us build that bridge. We're looking for an engineer who reasons from first principles, flourishes with ownership in a fast-paced environment, and uses AI with sound judgment. What you’ll be doing: Lead the effort across multi-functional teams to keep the program’s power and thermal productization strategy clear, executable, and on track. Create methodology and silicon test plan based controller designs and architecture, including characterization process, debug tools, fuse/firmware settings and lab requirements. Drive resolution for challenging silicon issues through structured hypotheses, measurement plans, and root-cause closure. Steward the Power and Thermal playbook when the existing productization methodology

NVIDIA silicon runs the world's AI infrastructure. The frequency it delivers across every voltage, process corner, and workload is not assumed. It is measured, correlated, and validated. This role does that work. The Silicon Co-Design Group is where architecture intent becomes silicon reality. We own the boundary between what was designed and what was built, and we are the team that knows the difference. When a program ships at frequency and at quality, this team is a reason why. You will be the person who follows through between simulation and silicon. When the model is wrong, a frequency corner that doesn't hold, a Vmin that walks, a critical path that timing analysis missed, you find out why, and your data is what the rest of the program acts on. Architecture, design, and product teams do not guess. They use your numbers. The engineers who do this well are rare. They think like circuit designers, work like experimentalists, and reason like data scientists. If that is you, read on. What you'll be doing: Own silicon speed characterization from first power-on through production sign-off, covering frequency, Vmin, Vmax, and timing margins across the full PVT space. Close the correlation gap. Tie pre-silicon timing analysis and critical path predictions to measured silicon, quantify where the model diverges from reality, and produce analysis that architecture and design can act on with confidence. Trace failures to their source, whether a microarchitectural bottleneck, a critical path that doesn't close under voltage, a clocking issue, or a process corner the model didn't anticipate, and drive the resolution. Own and build AI agents that work at your direction: automated test orchestration, intelligent data pipelines, and analysis flows that expand coverage and compress cycle time without sacrificing difficulty. Know where AI accelerates real work and whe