Transportation Outbound Strategy Manager Jobs

GitLab is the intelligent orchestration platform for DevSecOps. GitLab enables organizations to increase developer productivity, improve operational efficiency, reduce security and compliance risk, and accelerate digital transformation. More than 50 million registered users and more than 50% of the Fortune 100* trust GitLab to ship better, more secure software faster. The same principles built into our products are reflected in how our team works: we embrace AI as a core productivity multiplier, with all team members expected to incorporate AI into their daily workflows to drive efficiency, innovation, and impact. GitLab is where careers accelerate, innovation flourishes, and every voice is valued. Our high-performance culture is driven by our values and continuous knowledge exchange, enabling our team members to reach their full potential while collaborating with industry leaders to solve complex problems. Co-create the future with us as we build technology that transforms how the world develops software. * Fortune 500® is a registered trademark of Fortune Media IP Limited, used under license. Claim based on GitLab data. Fortune 100 refers to the top 20% ranked companies in the 2025 Fortune 500 list, published in June 2025. Fortune and Fortune Media IP Limited are not affiliated with, and do not endorse products or services of GitLab. Backend Engineer, Monitoring and Anomaly Detection (Monetization) An overview of this role The Observability, Monitoring, and Integrations team sits within GitLab's Monetization section and owns end-to-end observability, monitoring, and detection across the systems that power how customers buy and use GitLab. As a Backend Engineer on the Fulfillment Workflow Monitoring (Catch All) team, you'll build and operate telemetry, detection, and reconciliation tooling that identifies billing, data, and event anomalies across CustomersDot, Salesforce, and Zuora before they affect revenue or the customer experience. This is a greenfield tea

GitLab is the intelligent orchestration platform for DevSecOps. GitLab enables organizations to increase developer productivity, improve operational efficiency, reduce security and compliance risk, and accelerate digital transformation. More than 50 million registered users and more than 50% of the Fortune 100* trust GitLab to ship better, more secure software faster. The same principles built into our products are reflected in how our team works: we embrace AI as a core productivity multiplier, with all team members expected to incorporate AI into their daily workflows to drive efficiency, innovation, and impact. GitLab is where careers accelerate, innovation flourishes, and every voice is valued. Our high-performance culture is driven by our values and continuous knowledge exchange, enabling our team members to reach their full potential while collaborating with industry leaders to solve complex problems. Co-create the future with us as we build technology that transforms how the world develops software. * Fortune 500® is a registered trademark of Fortune Media IP Limited, used under license. Claim based on GitLab data. Fortune 100 refers to the top 20% ranked companies in the 2025 Fortune 500 list, published in June 2025. Fortune and Fortune Media IP Limited are not affiliated with, and do not endorse products or services of GitLab. An overview of this role As a Backend Engineer on the GitLab Agent Observability team, you'll go beyond using AI tools and help define how we design, build systems that allow AI agents to interact with the full software delivery lifecycle, way beyond pure code creation. In this role you’ll contribute to the development of complex features and help establish architectural patterns both for how to interact with AI Agents across GitLab and how the resulting AI contributions manifest across GitLab. You’ll collaborate closely with engineers across the Agent Foundations stage and adjacent teams within AI engineering. This is a hi

GitLab is the intelligent orchestration platform for DevSecOps. GitLab enables organizations to increase developer productivity, improve operational efficiency, reduce security and compliance risk, and accelerate digital transformation. More than 50 million registered users and more than 50% of the Fortune 100* trust GitLab to ship better, more secure software faster. The same principles built into our products are reflected in how our team works: we embrace AI as a core productivity multiplier, with all team members expected to incorporate AI into their daily workflows to drive efficiency, innovation, and impact. GitLab is where careers accelerate, innovation flourishes, and every voice is valued. Our high-performance culture is driven by our values and continuous knowledge exchange, enabling our team members to reach their full potential while collaborating with industry leaders to solve complex problems. Co-create the future with us as we build technology that transforms how the world develops software. * Fortune 500® is a registered trademark of Fortune Media IP Limited, used under license. Claim based on GitLab data. Fortune 100 refers to the top 20% ranked companies in the 2025 Fortune 500 list, published in June 2025. Fortune and Fortune Media IP Limited are not affiliated with, and do not endorse products or services of GitLab. An overview of this role As a Support Engineer at GitLab, you'll sit at the intersection of Support and Engineering, helping customers solve complex, real-world challenges while running GitLab in diverse and demanding environments. You'll join the Engineering department and work directly with customers as they encounter edge cases. You'll dig into Linux systems, logs, and our Ruby on Rails codebase to troubleshoot performance issues, reproduce bugs, and contribute merge requests that fix problems at the source. You'll also improve our documentation, refine support processes in our issue tracker, and collaborate closely with Produ

We believe that the way people interact with their finances will drastically improve in the next few years. We’re dedicated to empowering this transformation by building the tools and experiences that thousands of developers use to create their own products. Plaid powers the tools millions of people rely on to live a healthier financial life. We work with thousands of companies like Venmo, SoFi, several of the Fortune 500, and many of the largest banks to make it easy for people to connect their financial accounts to the apps and services they want to use. Plaid’s network covers 12,000 financial institutions across the US, Canada, UK and Europe. Founded in 2013, the company is headquartered in San Francisco with offices in New York, Seattle, Washington D.C., Raleigh, London, and Amsterdam. Our Fraud Intelligence team's mission is to turn fraud signals into insight that our EPD teams transform into improvements across Protect, IDV, Signal, and Guaranteed Payments. We believe transaction patterns, device signals, identity linkages, and behavioral data are dramatically underleveraged tools in fraud prevention, and we ground our products in what adversaries are actually doing right now. As the Fraud Intelligence Lead, you will build and run a small, high-leverage team of Fraud Intelligence Analysts (and eventually a Staff Researcher) responsible for live casework across Protect, IDV, and Payments/ACH. You'll operate as a player-coach, hiring and coaching your team while staying close enough to the work to personally pick up casework and SEV response when needed. Responsibilities Team Building & People Leadership Set the casework quality bar: define what rigorous investigation, triage, and reporting look like for the team Coach analysts on investigation technique, pattern synthesis, and translating findings into product/model input Operating Model & Cross-PA Partnership Own coverage allocation across the Protect/IDV and Payments/ACH pods, including flexing assign

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities 12+ years in Design Verification (experience with DDR/GDDR/DDR memory Verification is preferred) Define and drive verification architecture and methodology for next generation DDR designs. Develop verification plans, coverage strategies, and sign-off criteria. Architect and implement UVM-based testbenches and reusable verification components. Collaborate strictly with build teams to ensure verification completeness and quality. Mentor and guide verification engineers on guidelines and advanced methodologies. Evaluate and integrate AMS Co-Simulation techniques for mixed-signal IP verification. Work closely with EDA vendors to adopt the latest tools and flows. Leverage AI/ML tools to improve verification efficiency and debug turnaround time Develop or utilize AI-assisted regression analysis tools for failure classification Apply data-driven techniques to identify patterns in verification failures and silicon risks Contribute to automation initiatives such as Intelligent test generation, predictive coverage gap analysis, AI-driven waveform/debug analytics Required Skills & Qualifications Expert-level proficiency in SystemVerilog, UVM, and advanced verification methodologies. Familiarity with AMS Co-Simulation and mixed-signal verification flows (preferred). Hands-on experience with simulation, coverage analysis, and r

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities: Develop and standardize EMIR methodology that applies consistently across all DRAM products, ensuring alignment, repeatability, and high-quality analysis outcomes Perform static and dynamic EM/IR and PDN analysis using RedHawk or Totem or other industry‑standard tools; identify root‑cause issues such as high‑resistance segments, insufficient via density, and decap deficiencies, and provide clear, actionable recommendations to design and layout teams. Actively leverage AI‑based tools, agentic workflows, and automation frameworks for effective Power-delivery-network (PDN) analysis. Maintain a strong understanding of the full EMIR flow—from netlist preparation, extraction, simulation, and debug to reporting and silicon correlation—and ensure accurate evaluation across operating modes and temperatures. Partner across design, timing, physical implementation, architecture, modeling, and verification teams to understand real switching behavior, develop worst‑case vectors, and standardize analysis expectations across global teams. Collaborate with cross-geographical teams and also EDA tool vendors to evaluate and improve EMIR methodologies, and document Best Known Methods (BKMs) to enhance consistency and correlation across DRAM teams. Develop and maintain dashboards to track EMIR results, monitor trends, and support signoff progression for multiple designs. Qualifications: Master’s degree i

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an interconnect modeling CAD engineer, you will be responsible for developing new flows and methodologies for extracting and releasing interconnect models used by EDA tools for extracting layout parasitics for accurate prediction of electrical behavior of designed circuits. As part of this effort, you will also be working with the Scribe TEG team to design and develop new test structures used for the extraction. You will also be interacting with the external EDA tool vendors to improve those flows as necessary, and support Micron designers in using the tools and flows. インターコネクトモデリングのCADエンジニアとして、EDAツールによるレイアウト寄生要素の抽出や、設計回路の電気的特性を正確に予測するために使用されるインターコネクトモデルの抽出・リリースに向けた新しいフローや手法の開発を担当します。 この取り組みの一環として、Scribe TEGチームと協力し、抽出に必要な新しいテスト構造の設計・開発を行います。さらに、必要に応じて外部EDAツールベンダーと連携し、フローの改善を進めるほか、Micronの設計者がツールやフローを円滑に利用できるようサポートします。 Build and release interconnect models based on process technology information for use by parasitic extraction tools to extract layout parasitics. Work with the process technology development team members located at global sites to acquire details concerning the interconnect stack so that accurate interconnect models can be released. Work with the process technology development and scribe TEG design team s located at global sites to develop methodologies and design TEGs for properly calibrating interconnect models. Develop new flows and methodologies for parasitic extraction from layout. Work with ex

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, we're not just designing chips. We're building the physical architecture that powers artificial intelligence, accelerates cloud computing, enables autonomous vehicles, and connects the world through mobile and edge devices. Every breakthrough in AI — from large language models to next-generation data centers — runs on memory. And every bit of that memory lives inside a package that someone like you designs! We're looking for a Senior Package Design Engineer who is passionate about sadvanced semiconductor packaging and ready to lead at the intersection of silicon, system, and scale. This is a high-impact, highly visible role where you'll work across the full product lifecycle — from early-stage co-design with silicon teams all the way to High Volume Manufacturing (HVM). If you thrive where precision meets innovation, where your decisions shape products reaching millions of users worldwide, and where your expertise directly influences how the AI era unfolds — this role is for you! Responsibilites: Lead Co-Design from Silicon to System - Partner with silicon design, Business Units, customers, and package architecture teams to define new product concepts from the earliest stages of chip development - Optimize die floorplans, interconnection schemes, and package architectures — from concept to HVM - Drive trade-off studies and architecture decisions for advanced DRAM products targeting AI/D

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities and Tasks General Expectations: Contribute to group objectives and drive projects with limited supervision. Continuously evaluate and refine approaches and goals. Implement and transfer processes across teams and sites. AI adaptation such as u sing Artificial Intelligence, applying Artificial Intelligence to daily tasks and create Intelligence agents to aid projects Specific Expectations: Define reticle specifications in collaboration with MTC for each node series. Ensure fracture teams apply best-known methods and correct misuse of techniques. Support tapeout teams in implementing new data preparation flows. Evaluate long-running fracture jobs that do not meet performance goals. Fulfill internal reticle material requests using standard production flows. Troubleshoot CD Metrology issues prior to OPC production handoff. Resolve integration issues using OPC procedures and identify recipe/process interactions. Provide feedback to OPC management for innovative improvements. Mentor peers by sharing hands-on knowledge beyond standard training. Deliver quality, timely results for significant projects with high impact. Foster positive interactions with team members, other departments, and suppliers. Ownership and Continuous Improvement: Evaluate issues and implement improvements in toolsets or pr

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Operations Central Team (OCT) Diffusion/Implant Manufacturing Alignment Senior Engineer/Staff Engineer will drive tool and process optimization, global manufacturing alignment, and preventive maintenance standardization across the Micron network. This role will collaborate with equipment and process engineering teams to improve tool utilization, develop safe shutdown and recovery procedures, deploy equipment and process BKMs, and sustain global standards through systems such as SEAL. The position requires strong technical experience in the Diffusion or Implant area, problem-solving capability, effective cross-functional communication, and the ability to support AI-assisted data analysis and workflow improvement. Take on an outstanding opportunity at Micron, where new ideas meet outstanding quality. As an OCT Diffusion/ Implant MFG Alignment Sr Engineer/ Staff Engineer in Hiroshima, you will maintain and improve our innovative manufacturing systems and methods. Collaborate with a group that shares your passion for detail and your aim to achieve international excellence! Responsibilities: Improve tool utilization to meet world-class standards by refining processes that eliminate underutilized tools and enable cost savings through strategic cold/warm shutdowns. Develop globally aligned warm shutdown procedures that ensure safety and flawless recovery to production. Standardize practices and proven methods (BKMs) across process areas by establishing global alignment tea

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Design Engineer at Micron Technology, Inc., you will be responsible for designing and analyzing digital and analog circuits used in the development of memory products! We are engaged in developing groundbreaking silicon-to-systems solutions – right from technology development and advanced memory designs to product development, systems design and validation resulting in world class memory solutions! In this position, you will collaborate with Micron’s various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction. You will own physical implementation and top-level integration of large digital designs in our NAND products. Drive blocks and full-chip partitions through synthesis handoff, floorplan, place-and-route, and timing/DRC/LVS closure. Perform hierarchical design planning and top-level assembly. Responsibilities will include, but are not limited to: Contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits Parasitic modeling and assisting in design validation, reticle experiments and required tape-out revisions Leading all aspects of and managing the layout process including floor-planning, placement, and routing

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our Data Center Corporate Marketing team connects Micron’s technology leadership to the market through clear, compelling storytelling. We work at the intersection of content, analytics, and global execution—bringing innovations in memory and storage to life for customers building the future of data infrastructure. Join a collaborative, high-impact team that shapes how Micron shows up in the data center and AI ecosystem! We are seeking a Data Center Corporate Marketing Campaign Lead to own the end-to-end strategy and execution of integrated, global campaigns. This role is central to turning corporate priorities into impactful, audience-led campaigns that deliver measurable results. You will orchestrate cross-functional teams, create compelling content, and use data and AI-driven insights to optimize campaign performance and elevate Micron’s brand. Responsibilities: Lead end-to-end data center campaign strategy, execution, and performance measurement across global markets Translate corporate narratives into clear campaign objectives, messaging, content, and activation plans Orchestrate cross-functional teams and agency partners to ensure consistent messaging and on-time delivery Develop audience-focused content aligned to industry trends, use cases, and product proof points Monitor campaign performance, drive optimization, and deliver insights for continuous improvement </ul

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. What’s Encouraged Daily: AI-First Engineering: Deploy AI tools (LLMs, code/RTL generation, spec parsing, waveform interpretation, layout engines) as default practice. Continuously identify automation opportunities and rearchitect workflows—specs, simulations, reviews, hand-offs—to be AI-consumable. Build prompt libraries, agents, and scripts that eliminate recurring manual patterns! AI Leadership: Champion AI adoption by evaluating emerging tools, running pilots, and publishing standard methodologies that measurably reduce cycle time or prove quality! Technical Ownership: Design and verify major IO/datapath blocks (receivers, serializer, clock distribution, equalizers, ZQ calibration, ONFI training, wave pipelines) to meet performance specs, using AI to accelerate exploration, sizing, and verification. Multi-functional Collaboration: Work with integration, design, and Apps teams to define interfaces and evaluate new specifications. Use AI to summarize discussions, reconcile specs, and quantify trade-offs. Mentorship: Document AI-augmented methodologies and teach engineers to work in an AI-first environment—not just which tools to use, but how to rethink engineering with AI. Minimum Qualifications: BS/MS in Electrical Engineering with 8&#43; years IC design experience Hands-on AI tool usage (LLM assistants, coding copilots, agentic workflows, ML-based EDA) with concrete examples of productivity or design impact Experience redesig

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Boise Facilities team supports the critical infrastructure that keeps site operations running smoothly and efficiently. The team works on complex systems that directly impact uptime, safety, and manufacturing performance. It’s a highly collaborative environment where engineering expertise drives real impact! The Senior/Staff Facilities SCADA Engineer plays a key role in designing, maintaining, and improving automation systems that power facility operations. This individual brings deep PLC and SCADA expertise to ensure reliability, scalability, and integration across systems. The role partners closely with engineering, operations, and vendors to support commissioning, solve issues, and lead continuous improvement efforts. Responsibilities: Design, develop, and maintain PLC programs using Siemens Step 7, TIA Portal, and FasTrak 505 Workshop Configure and support HMI applications using AVEVA System Platform OMI Lead deployment and fixing of Siemens automation hardware across platforms Partner with multi-functional teams to support system reliability, performance, and commissioning Document PLC code, system changes, and configurations Use Agentic AI to improve current process workflows and drive continuous improvement Minimum Qualifications: Bachelor’s degree in Controls Engineering or related field, or equivalent experience 5&#43; years of PLC programming, hardware, and

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. OUR VISION To redefine the global use of information, enriching life for everyone. Micron Technology is an industry leader in memory and storage solutions, enabling the acceleration of information into actionable intelligence and fostering rapid progress in learning, communication, and technological development. Department Introduction The Firmware & Product Test (FPT) team at Micron Technology holds a pivotal role in validating firmware specifications for SSDs. The team develops comprehensive verification plans, implements them using Python, and ensures strict adherence to NVMe standards and security protocols. Testing methodologies include white-box, grey-box, and black-box approaches conducted on a module-by-module basis throughout firmware development and integration. Validation occurs across multiple environments, including simulation, FPGA prototyping, and prototype hardware. Key Responsibilities Develop and execute firmware verification plans for customer specifications and NVMe protocols used in enterprise SSDs, with emphasis on front-end features such as SMART, Trim, Get Log Page, and OCP. Design and implement grey-box, white-box, and black-box test methodologies to verify firmware functionality and robustness. Analyze failures from weekly regressions, perform root-cause analysis, and clearly document findings with guidance from senior engineers. Contribute to test development, execution, automation,