Verification Of Benefits Specialist Jobs

At Jamf, we believe in an open, flexible culture based on respect and trust. Our track record and thriving work environment all stem from the freedom we grant ourselves to get the job done right. We take pride in helping tens of thousands of customers around the globe succeed with Apple. The secret to our success lies in our connectivity, while operating with a high degree of flexibility. Work-life balance remains our priority while feeling connected is important to maintain our strong culture, achieve our goals, and thrive as #OneJamf. This role is offered as a remote in Poland . We are only able to accept applications for those based in Poland or who have sponsorship to live and work in Poland . You may be required to work periodically at a Jamf office or collaborative work location with other Jamf employees in your area for certain events or moments that matter. What you'll do at Jamf : At Jamf, we empower people to be their best selves and do their best work. As a Software Engineer II on a new team enabling secure, governed adoption of autonomous and agentic workflows, you'll help build production systems where AI agents do real work on real code - authoring changes inside deterministic gates, with independent verification and a full audit trail. This is a greenfield build inside a mature platform, starting with Security. What you can expect to do in this role: Build the production systems where AI agents do real work on real code – authoring changes that run inside deterministic gates, with independent verification and a full audit trail behind every one. Take customer and platform problems, break them into workable pieces with your agile team, and own most of them end to end. Draw the line on autonomy: design the trust boundaries, blast radius, and least-privilege model for the automation itself, which holds elevated access to production. Build the evaluation and observability

At Jamf, we believe in an open, flexible culture based on respect and trust. Our track record and thriving work environment all stem from the freedom we grant ourselves to get the job done right. We take pride in helping tens of thousands of customers around the globe succeed with Apple. The secret to our success lies in our connectivity, while operating with a high degree of flexibility. Work-life balance remains our priority while feeling connected is important to maintain our strong culture, achieve our goals, and thrive as #OneJamf. This role is offered as a hybrid in Brno, the Czech Republic . We are only able to accept applications for those based in the Czech Republic or who have sponsorship to live and work in the Czech Republic . What you'll do at Jamf : At Jamf, we empower people to be their best selves and do their best work. As a Software Engineer II on a new team enabling secure, governed adoption of autonomous and agentic workflows, you'll help build production systems where AI agents do real work on real code - authoring changes inside deterministic gates, with independent verification and a full audit trail. This is a greenfield build inside a mature platform, starting with Security. What you can expect to do in this role: Build the production systems where AI agents do real work on real code – authoring changes that run inside deterministic gates, with independent verification and a full audit trail behind every one. Take customer and platform problems, break them into workable pieces with your agile team, and own most of them end to end. Draw the line on autonomy: design the trust boundaries, blast radius, and least-privilege model for the automation itself, which holds elevated access to production. Build the evaluation and observability that keeps non-deterministic systems honest – measuring accuracy and catching silent degradation before anyone else

Secure Every Identity, from AI to Human Identity is the key to unlocking the potential of AI. Okta secures AI by building the trusted, neutral infrastructure that enables organizations to safely embrace this new era. This work requires a relentless drive to solve complex challenges with real-world stakes. We are looking for builders and owners who operate with speed and urgency and execute with excellence. This is an opportunity to do career-defining work. We're all in on this mission. If you are too, let's talk. Secure Every Identity, from AI to Human Identity is the key to unlocking the potential of AI. Okta secures AI by building the trusted, neutral infrastructure that enables organizations to safely embrace this new era. This work requires a relentless drive to solve complex challenges with real-world stakes. We are looking for builders and owners who operate with speed and urgency and execute with excellence. This is an opportunity to do career-defining work. We're all in on this mission. If you are too, let's talk. About Okta Verify Team The Okta MacOS platform team is responsible for building Okta's MacOS Apps and SDKs. The Okta Verify app allows you to securely access your apps via 2-step verification, ensuring that you, and only you, can access your app accounts. It integrates with MacOS system features by communicating with our backend to and grant proper application access. Position Overview As a Senior SET, you will take end-to-end ownership of the test strategy, execution, and quality assurance for the Okta Verify macOS app, filling a critical gap as our existing framework scales to support advanced Apple feature sets. You will work closely with local engineers and cross-functional US-based mentors to design, build, and optimize scalable automation frameworks that completely replace manual testing validation for critical macOS authentication components. This role requires in-depth understanding of macOS system internals, native app archit

Who we are About Stripe Stripe is a financial infrastructure platform for businesses. Millions of companies—from the world's largest enterprises to the most ambitious startups—use Stripe to accept payments, grow their revenue, and accelerate new business opportunities. Our mission is to increase the GDP of the internet, and we have a staggering amount of work ahead. That means you have an unprecedented opportunity to put the global economy within everyone's reach while doing the most important work of your career. About Stripe Stripe is a financial infrastructure platform for businesses. Millions of companies - from the world’s largest enterprises to the most ambitious startups - use Stripe to accept payments, grow their revenue, and accelerate new business opportunities. Our mission is to increase the GDP of the internet, and we have a staggering amount of work ahead. That means you have an unprecedented opportunity to put the global economy within everyone's reach while doing the most important work of your career. About the team The Product Design team defines and delivers user-facing experiences across Stripe. Product Designers work closely with engineers, product managers, researchers, strategists, operations, data scientists, and marketers to shape products from early strategy through launch and iteration. You'll join the Risk team, where design shapes how businesses get started on Stripe, stay compliant, and grow with confidence. Stripe's ability to innovate, expand globally, and serve the world's most ambitious companies depends on world-class risk management. But great risk management requires clear, trustworthy, and surprisingly well-crafted experiences during some of the most important moments in a user's relationship with Stripe. From onboarding and verification to account health, your work will help users understand what's happening, know what to do next, and feel confident that Stripe is growing with them as a trusted partner. Risk at Stripe is also ev

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for a software engineer to help build the design methodology, software abstractions, and infrastructure that enable a small silicon team to develop complex chips rapidly and with high confidence. You will turn evolving architecture and design needs into reusable tools and workflows that improve iteration speed, quality, and then apply those tools to help construct world-class silicon. You’ll work closely across architecture, design, verification, performance modeling, and systems software. This role is well suited for an engineer who enjoys building high quality software and is motivated by the challenge of improving velocity and quality of the silicon development process. In this role, you will: Develop and scale design methodologies for rapid first-party chip development and apply them to construct complex custom chips Create abstractions that allow hardware structures, configurations, experiments, and results to be represented consistently across tools. Automate high-value engineering workflows and improve their reproducibility, observability, testability, and ease of use. Partner with architects, RTL designers, verification engineers, compiler engineers, and systems software engineers to gather requirements and then implement solutions. Use methodology and tooling to identify design risks early, accelerate iteration, and improve confidence in performance and implementation tradeoffs. Contribute across multiple aspects of software and hardware

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale. This is a senior, hands-on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure, physical design convergence, bring-up, and production readiness. You will plan and oversee the work of junior engineers and help drive and develop productive engineering relationships with external partners and help manage partner execution. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic as well as off-chip protocol bridges and interfaces. Drive third party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and de

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role You will develop and evolve the tooling ecosystem that hardware engineers rely on every day — from hardware compilers and IR transformations to simulation, debugging, and automation infrastructure. The work spans software engineering, compiler concepts, and practical hardware workflows, with direct impact on how quickly and effectively we design next-generation AI systems. You’ll collaborate closely with architects, RTL designers, and verification engineers to translate real engineering friction into durable, scalable tooling solutions. In this role you will: Build and improve the software tooling that makes hardware teams faster: compilation, IR transforms, RTL generation, simulation, debug, and automation. Extend and integrate hardware compiler stacks (frontends, IR passes, lowering, scheduling, codegen to Verilog/SystemVerilog) and connect them to real design workflows. Improve developer experience and reliability: reproducible builds, better error messages, faster iteration loops, and dependable CI and regression infrastructure. Work closely with designers and verification engineers to turn real pain points into durable tools. Dive into RTL when needed: read and reason about Verilog/SystemVerilog to debug issues, validate tool output, and improve debuggability. Be willing to go all the way down the stack when necessary, including gate-level views, synthesis results, and implementation artifacts. Help enable PPA optimization loops by building analysis and au

Position Summary: We are seeking an experienced and dynamic Associate/Senior Associate – Vendor Onboarding to join our Procurement Operations team. The ideal candidate will have strong experience in Vendor Management, SAP MM, SaaS-based Procurement Platforms, MS Office, reporting, and stakeholder coordination. The role will be responsible for managing end-to-end vendor onboarding activities, coordinating with suppliers and internal stakeholders, ensuring compliance, and driving process efficiency through data analysis and reporting. Key Responsibilities: Vendor Onboarding & Management  Manage end-to-end vendor onboarding processes, including document collection, verification, due diligence, and system registration.  Coordinate with vendors through calls, emails, and meetings to ensure timely completion of onboarding requirements.  Ensure vendor master data accuracy and compliance with organizational policies.  Support vendor lifecycle management activities, including updates and maintenance of vendor records. SAP & Procurement Operations:  Work extensively on SAP MM and SaaS-based procurement platforms for vendor onboarding and master data management.  Coordinate between procurement, finance, compliance, and business teams to facilitate smooth onboarding.  Resolve onboarding-related issues and provide operational support to stakeholders. Dashboard & Reporting  Develop and maintain management dashboards, MIS reports, and performance trackers using MS Excel and other reporting tools.  Analyze onboarding metrics and generate actionable insights for management.  Monitor onboarding turnaround times and identify opportunities for process improvement. Stakeholder Management  Collaborate with internal business stakeholders to understand onboarding requirements and provide timely support.  Maintain strong relationships with vendors and internal teams.  Ensure effective communication and follow-up with all stakeholders to achieve onboarding targets. Require

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The US Expansion Construction team is driving some of the most significant semiconductor manufacturing projects in the United States, including two high-volume manufacturing facilities in Boise, Idaho (ID1 and ID2) and a greenfield manufacturing facility in Clay, New York. Our team partners across engineering, construction, commissioning, and operations to deliver world-class facilities that support the future of technology and innovation. As the ID Quality Assurance Lead, you will be a key member of the US Expansion Strategic Programs team, reporting to the ID Sr. Commissioning Manager. In this highly visible role, you will lead quality governance across major capital projects, ensuring compliance, commissioning readiness, documentation integrity, and operational turnover excellence. You will serve as the primary owner-side quality leader, collaborating with contractors, vendors, inspection agencies, operations teams, and regulatory stakeholders to deliver successful project outcomes. Responsibilities: Lead quality governance, performance metrics, audit programs, reporting, and continuous improvement initiatives across Idaho capital projects Oversee contractor and vendor quality execution, including quality plans, inspections, testing, material verification, hold points, and compliance with project requirements Manage special inspection programs, testing agency coordination, regulatory interfaces, and turnover-ready quality documentation Align construction quality activities with co

Job Title AI Senior Systems Engineer (AI for RAMS & Systems Engineering) Job Description As an AI Senior Systems Engineer, you will help shape the future of Systems Engineering at Philips by driving the application of Artificial Intelligence within Systems Engineering and Reliability, Availability, Maintainability and Safety Engineering (RAMS) practices. You will identify opportunities where AI can enhance engineering activities, improve engineering productivity, and increase the quality, consistency, and traceability of engineering deliverables throughout the product development lifecycle. Acting as a thought leader and trusted advisor, you will help engineering teams understand, adopt, and effectively apply AI technologies within their daily engineering work. Working closely with systems engineers, RAMS engineers, architects, software teams, and AI specialists, you will bridge the gap between engineering challenges and emerging AI capabilities. You will contribute to the evolution of engineering methodologies, tools, and best practices that enable the next generation of AI-enabled Systems Engineering and RAMS Engineering at Philips. Your role: Drive the adoption of AI within Systems Engineering and RAMS practices across Philips. Identify, develop, and scale AI use cases for requirements engineering, system architecture, modelling, verification, validation, traceability, and engineering knowledge management. Identify, develop, and scale AI use cases for RAMS engineering like FMEA, data analysis, HALT/ALT, Modelling Simulation & Analysis, for Hardware and Software Support engineering teams in evaluating and implementing AI-enabled engineering workflows, methods, and tools. Coach and educate Systems Engineers, RAMS Engineers, Architects, and technical leaders on the opportunities, limitatio

Job Details: Job Description: Join an enthusiastic team of engineers in Intel's Networking Solutions Group (NSG) focused on enabling next generation of programmable Infrastructure Processing Units (IPUs) with our lead customers as part of the Customer Experience Support (CES) organization. Intel brings decades of leadership in networking, virtualization, packet processing, storage, and security to a new class of IPU products that accelerate host networking functions and support emerging use cases such as security, virtualization, storage, load balancing, and data path optimization. Working closely with major cloud service providers and Intel development teams, you will help deliver customized IPU based solutions that enhance isolation, security, performance, storage and system management for our customers. A big part of the day-to-day job is to help customers manage feature request processes, enable solutions, and debug issues. Projects and responsibilities include but are not limited to: • Gain our customers' trust, understand their needs, and build POCs to meet them. Work closely with internal and external partners to understand use cases and requirements. • Be the go-to technical resource for customers building complex Datacenters, AI infrastructure as well as helping them understand performance characteristics for solutions. • Prepare and deliver technical content to customers including presentations, workshops, etc. • Contribute across the full IPU lifecycle, including board and platform bring up, low-level device initialization, OS driver and kernel configuration, system management, feature enablement, use case testing, debugging, and verification. • Defines systems implementation and integration solutions and plans to ensure optimum performance and reliability across hardware, firmware and software w

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Principal ASIC Design Engineer About the Role At Micron, we transform how the world uses information to enrich life for all. As a global leader in memory and storage innovation, we develop technologies that accelerate intelligence and enable the next era of AI, ML, and advanced computing. Micron’s Interface Pathfinding team drives performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3–5 year technology horizon. A core part of that work is silicon-based validation of novel PHY solutions, and we are growing the team to execute. As the Principal ASIC Design Engineer , you will be the primary digital contributor on a deliberately small, senior team — united around the goal of carrying high-speed interface technologies from architecture to tape-out. The team’s analog and chip-level architecture is anchored by a deeply experienced analog custom design engineer; your role is to be the authoritative digital voice — owning RTL design and micro-architecture of the digital blocks, defining timing constraints, supporting verification, and serving as the key interface between the digital design and the analog and layout specialists who will carry the implementation through to silicon. On a test ASIC of this scope, the front-end digital work is the critical path, with contractor and layout support engaged as bandwidth demands warrant. What You’ll Own Digital Block Architecture & RTL Design Own the micro-architecture and RTL implement

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. MTS, Interface Pathfinding Hardware Development Engineer About the Role At Micron, our vision is to transform how the world uses information to enrich life for all. As a global leader in memory and storage innovation, we develop technologies that accelerate intelligence and enable the next generation of high-speed interfaces. Micron’s Interface Pathfinding team drives performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3–5 year technology horizon. As the Interface Pathfinding Hardware Development Engineer , you will own characterization for a high-speed interface test-chip program: the characterization plan and its success criteria, development of the characterization bench hardware and its automation, the measurement-uncertainty budget, and the correlation report proving the silicon matches the models. You will join a small, senior team spanning analog design, layout, digital design, and verification, working closely with the Chip Lead and the Signal Integrity and Physical Design engineers — driving decisions independently while consulting heavily with other experts across Micron. This is a foundational hire for a growing program. Strong execution early is expected to lead to follow-on projects of increasing scope, team size, and characterization complexity — including an expanding mandate for AI-enabled engineering leadership across the organization. What You’ll Own Characterization Planning • Derive the electr

Work Flexibility: Hybrid or Onsite Stryker is hiring a Senior Quality Engineer to join our Neurovascular division. This is a hybrid r ole based in Fremont, CA or Salt Lake City, UT . As the Senior Design Quality Engineer , you will be actively involved in Product Risk Management, Post Market Surveillance, Design Control and Product Quality Improvement. You will be involved in a fast-paced mix of short design change efforts and will be responsible for product risk management and adherence to design control requirements throughout the product lifecycle. You will be responsible for ensuring that post market data and feedback is channeled into the risk management system throughout the product lifecycle. You will make regular use of problem-solving tools and statistical analysis to analyze and trend data and provide quality input into technical investigations, perform test method development and validation, design verification, risk assessment and design reviews. You will be responsible for supporting product testing and failure analysis, writing protocols and reports, creating and maintaining risk files and assessing the impact of necessary changes to our products. You will lead initiatives to increase sales and improve the customer experience of our devices. Neurovascular (NV) products push the boundaries of technology to meet ever increasing product performance requirements, making the goal of assessing and demonstrating, safety, performance and compliance an exciting challenge. What You Will Do Develop qualification plans, protocols, and reports for new products, existing products, components, and subassemblies. Execute product testing, inspection, verification, and validation activities to support design and quality objectives. Perform failure investigations and root cause anal

About Graphcore Graphcore is a global leader in artificial intelligence computing systems. We design advanced semiconductors and data center hardware that deliver the specialized processing power needed to advance AI while improving the efficiency required for broad adoption. As part of SoftBank Group, Graphcore belongs to a family of companies developing some of the world’s most transformative technologies. Our new AI Engineering Campus in Austin will play a central role in building the future of AI computing. The Opportunity As a Mechanical Engineering Intern, you will contribute to the mechanical design and thermal validation of advanced AI hardware. Working alongside experienced mechanical and thermal engineers, you will gain hands-on experience with 3D computer-aided design (CAD), laboratory setup, test development, prototype evaluation, and engineering documentation. Type: 12-week summer internship Timing: May - August (exact dates to be confirmed) Commitment: Full-time What You’ll Do Contribute to mechanical design activities using Creo or comparable 3D CAD software, including part modeling, assemblies, drawings, and design updates under the guidance of experienced engineers. Work with the thermal engineering team to develop test procedures and help set up laboratory capabilities for evaluating AI hardware. Support thermal and mechanical testing using appropriate laboratory equipment; collect, organize, and analyze test data. Assist the mechanical and thermal design teams with prototype evaluation, troubleshooting, design verification, and documentation of findings. Collaborate with cross-functional engineering partners, communicate progress and issues clearly, and follow applicable laboratory and safety procedures. What You’ll Bring Current enrollment in a bachelor's, master's, or doctoral program in mechanical engineering or a related discipline during the internship. Students in other disciplines with relevant mechanical engineering exper