Advanced Analytics Lead in United States

1671 About the Role We are seeking a Senior Signal Integrity Engineer to develop, validate, and optimize high-speed signaling solutions across blade- and rack-level architectures for advanced compute platforms. This role sits at the intersection of silicon, package, interconnect, board, and system design , with a strong emphasis on hands-on measurement, simulation correlation, and cross-functional technical communication. Key Responsibilities End-to-end signal integrity analysis for blade- and rack-level system architectures. Analyze and optimize high-speed and low-speed I/O interfaces, including PCIe Gen4/5/6, Ethernet, DDR, SerDes, SPI , I2C, etc . and related interconnects. Perform time-domain and frequency-domain simulations using tools such as Ansys HFSS, Keysight ADS, Cadence Sigrity, CST, SPICE , or similar. Support hands-on lab validation using VNA, TDR, BERT, and high-speed oscilloscopes . Correlate simulation results with lab measurements to identify margin gaps, debug issues, and improve design methodology. Collaborate with silicon, package, board, connector, cable, and system design teams to optimize I/O channel performance. Work with interconnect vendors and ODMs to guide board layout, stack-ups, routing rules, and system design decisions. Review schematics, layouts, simulation results, and validation data for blade, backplane, and rack-level hardware. Prepare and communicate clear validation reports, measurement summaries, debug findings, and technical recommendations to internal teams, vendors, and senior technical stakeholders. Required Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field . Strong experience in signal integrity for high-speed digital systems. Hands-on measurement expertise using VNAs, TDRs, BERTs, and high-speed oscilloscopes . Experience measuring and analyzing S-parameters, impedance profiles, eye diagrams, jitter, timing margins, insertion loss, return loss, and cro

About the Team OpenAI’s Industrial Compute team is building and productizing infrastructure capabilities that help organizations deploy and operate advanced AI systems at scale. The team works across AI hardware, systems engineering, physical infrastructure, and customer delivery to turn emerging technologies into reliable, repeatable infrastructure solutions. Our work sits at the intersection of technical strategy, product development, engineering, and deployment. We partner closely with customers and internal engineering teams to solve complex infrastructure challenges spanning compute, power, cooling, controls, and facility efficiency. About the Role We are seeking a senior, hands-on Data Center Infrastructure Architect to develop and optimize the physical infrastructure required for large-scale AI deployments. This is a broad technical role spanning data center architecture, electrical and mechanical systems, high-density compute, controls, telemetry, and digital modeling. You will use simulation, operational data, and digital-twin approaches to evaluate infrastructure designs, identify system-level constraints, and improve efficiency, reliability, cost, and speed of deployment. The ideal candidate can move fluidly between first-principles analysis, facility and equipment design, computational modeling, engineering review, and real-world implementation. You should be comfortable working across disciplines rather than operating solely within electrical, mechanical, or software boundaries. Key Responsibilities Define system-level architectures for high-density AI data centers across power, cooling, IT equipment, controls, and facility infrastructure. Develop digital twins and other computational models that represent the behavior of data center systems under changing workloads, environmental conditions, equipment configurations, and failure scenarios. Use design and operational data to identify constraints, improve PUE and related efficiency metrics, and optimize

About the Team: OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. In this role you will: As a Hardware Test Engineer, you will work on Machine Learning/AI hardware system projects to craft the solutions for current and future data center deployments. You will bring a strong understanding of hardware system testing, excellent project management skills, and the ability to collaborate across multiple teams to ensure efficient lab operations. You will be responsible for designing, implementing, and executing comprehensive test plans that ensure the reliability, performance, and scalability of our supercomputing hardware systems. You will develop detailed test plans and methodologies tailored to hardware components, including processors, memory modules, custom accelerators and interconnects. You will collaborate with hardware design, manufacturing, firmware teams and vendors to identify, analyze, and resolve issues affecting hardware, power, thermal and high-speed interconnects. You will perform in-depth debugging on the hardware system Excellent analytical skills to diagnose hardware issues, troubleshoot problems, and propose solutions. Ability to interpret complex test data, identify trends, and draw meaningful conclusions. High-speed links, with a focus on SerDes (Serializer/Deserializer) technology to assess signal integrity, error rates, and overall link performance. You will collaborate with the lab manager to maintain the equipment and hardware systems, including oscilloscopes, thermal test chambers, liquid cooling systems, and other mea

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale. This is a senior, hands-on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure, physical design convergence, bring-up, and production readiness. You will plan and oversee the work of junior engineers and help drive and develop productive engineering relationships with external partners and help manage partner execution. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic as well as off-chip protocol bridges and interfaces. Drive third party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and de

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role You will develop and evolve the tooling ecosystem that hardware engineers rely on every day — from hardware compilers and IR transformations to simulation, debugging, and automation infrastructure. The work spans software engineering, compiler concepts, and practical hardware workflows, with direct impact on how quickly and effectively we design next-generation AI systems. You’ll collaborate closely with architects, RTL designers, and verification engineers to translate real engineering friction into durable, scalable tooling solutions. In this role you will: Build and improve the software tooling that makes hardware teams faster: compilation, IR transforms, RTL generation, simulation, debug, and automation. Extend and integrate hardware compiler stacks (frontends, IR passes, lowering, scheduling, codegen to Verilog/SystemVerilog) and connect them to real design workflows. Improve developer experience and reliability: reproducible builds, better error messages, faster iteration loops, and dependable CI and regression infrastructure. Work closely with designers and verification engineers to turn real pain points into durable tools. Dive into RTL when needed: read and reason about Verilog/SystemVerilog to debug issues, validate tool output, and improve debuggability. Be willing to go all the way down the stack when necessary, including gate-level views, synthesis results, and implementation artifacts. Help enable PPA optimization loops by building analysis and au

About the Team: OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale. In this role you will: Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality. Define verification plans based on architecture and microarchitecture specs. Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies. Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness. Drive bug triage, root cause analysis, and work closely with design teams on resolution. Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments. You might thrive in this role if you have: BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification. Proven success verifying complex IP or SoC designs in industry-standard flows Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi). Strong knowledge

Ground Systems Integration Engineer (Experienced or Senior Level) Company: The Boeing Company Boeing Defense, Space & Security (BDS) is seeking a Ground Systems Integration Engineer (Experienced or Senior Level) to support an Air Dominance Fixed Wing Proprietary Program in Berkeley, MO . Step into a fast-paced, cutting-edge program where your expertise will drive the design, integration, and testing of advanced, cloud-based systems that empower mission planning, debrief, and tactical Command & Control (C2) solutions for fixed-wing platforms. As a key contributor, you will support the development, analysis, integration, and testing of innovative engineering solutions for critical Ground System capabilities, including but not limited to: Mission Planning and Debrief Command and Control Systems Network and Communication Architectures Situational Awareness Enhancements You will take ownership of developing prioritized mission systems digital threads, ensuring seamless support for ground systems from initial design through to final delivery. You will work with a high-performing, cross-functional team in an agile environment, driving next-generation capabilities from design through delivery. This role offers the chance to innovate with open-architecture, model-based designs while collaborating across disciplines to support critical defense missions. If you’re passionate about advancing mission-critical systems and thrive in a collaborative, fast-moving environment, this is your opportunity to make a significant impact. Why Join Us? Impactful Work: Be part of a team that plays a crucial role in

Job Details: Job Description: About the Role Join a team developing next-generation CPU cores that power client, server, IoT, and AI platforms. As a Senior Physical Design Engineer (CPU), you will play a key role in delivering high-performance, power-efficient silicon solutions. You will take ownership of blocks within the CPU core design, driving implementation from RTL to GDS and contributing to advanced physical design methodologies. What You’ll Do Key responsibilities will include but not limited to: Own physical design and implementation of CPU core blocks or subsystems Execute synthesis, floorplanning, place and route, and design closure Perform static timing analysis (STA), power analysis, and physical verification Drive convergence of timing, power, and area (PPA) metrics Debug and resolve complex design issues across multiple design stages Develop and optimize design flows and automation scripts Collaborate cross-functionally with RTL design, verification, clocking, and full-chip teams Contribute to improving design methodologies and best practices Provide guidance to junior engineers where applicable Behavioral traits that we are looking for: Strong problem-solving and analytical thinking Takes ownership and accountability for deliverables Collaborates effectively across multidisciplinary teams Communicates technical concepts clearly and concisely Prioritizes work effectively in a fast-paced environment Continuously learns and applies new tools and methodologies Why Join Us Work on cutting-edge CPU core designs that power client, server, IoT, and AI platforms used worldwide Be part of

Quality Engineer (Associate or Experienced) Company: The Boeing Company Boeing Defense, Space & Security (BDS) has an exciting opportunity for a Quality Engineer to join our dynamic team in Berkeley, MO. Position Responsibilities: Represents Quality function on team activities to integrate contractual and Boeing Quality Management System requirements into all aspects of proposals and program processes and documentation Provides Quality interpretation of requirements Develops quality metrics, design and production certification plans for small programs to ensure compliance with contractual, Company and regulatory requirements Conducts capability assessments and process validations to support supplier selection activities Participates in various reviews to ensure quality attributes are incorporated into product designs Performs analysis, tests and process audits to ensure manufacturing and test readiness Provides material review dispositions for non-conformances Conducts RCCA and CAPA activities Analyzes non-conformance trends to evaluate effectiveness of corrective actions Recommends corrective actions to address non-conformances Performs benchmarking and other forms of analysis to ensure specified processes capability levels are achieved Supports Advanced Product Quality Planning (APQP) activities Works under general direction Basic Qualifications (Required Skills/Experience): Bachelor of Science degree from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), chemistry, physics, mathematics, data science, or computer scien

The Sec & Derivatives Sr Analyst is an intermediate level position responsible for processing orders and transactions originating from trading desks and branch offices in coordination with the Operations - Transaction Services team. The overall objective of this role is to facilitate the clearance, settlement and investigation of client securities and derivatives transactions. Responsibilities: Resolve complex process problems which require an in-depth evaluation of basic securities processing procedures and industry standards Process various hedge fund tasks, including calculating net asset value, reconciling cash and holdings, and pricing securities Offer advanced solutions for assigned securities processing areas Provide guidance and assistance to junior staff Oversee the set-up of new hedge funds, while representing a securities processing team, and acting as the analytical and procedural expert Serve as analytical or procedural expert for securities processing deliverables/initiatives Prepare expense budgets, analyze expense calculations, and prepare unaudited financial statements Ascertain fund value and allocate values to each investor Assist with the development of new techniques and streamlining hedge fund/securities processing activities Appropriately assess risk when business decisions are made, demonstrating particular consideration for the firm's reputation and safeguarding Citigroup, its clients and assets, by driving compliance with applicable laws, rules and regulations, adhering to Policy, applying sound ethical judgment regarding personal behavior, conduct and business practices, and escalating, managing and reporting control issues with transparency. Recommended Qualifications : 5-8 years of relevant experience Consistently demonstrates clear and concise written and verbal commun

Work Flexibility: Onsite It's Time to Join Stryker! Stryker is seeking a Staff Electrical Engineer to support the design and development of electrical systems and subsystems for complex medical devices. In this role, you will apply your electrical engineering expertise across design, prototyping, testing, troubleshooting, and documentation. You will translate product and customer needs into engineering requirements and robust electrical designs while collaborating closely with cross-functional teams throughout the product development lifecycle. What You Will Do Electrical Design and Development Design and develop electrical components, circuits, and subsystems for medical devices. Translate design inputs and system requirements into electrical engineering specifications and detailed designs. Develop, evaluate, and refine design concepts through analysis, prototyping, simulation, and bench testing. Apply advanced electrical test methods to evaluate component and subsystem performance. Investigate complex technical problems, identify potential solutions, and evaluate design alternatives against product and subsystem requirements. Conduct technical research, analysis, and engineering studies to support design decisions and product development. Assess system-level impacts and dependencies associated with electrical design choices. Verification and Technical Execution Develop and execute test methods to evaluate electrical designs, components, and subsystems. Analyze test results, troubleshoot design issues, and drive problems to root cause and resolution. Apply engineering analysis, modeling, simulation, and statistical methods as appropriate to support design decisions. Partner with other engineering dis

As a Research Scientist on our team, you will partner with Research Engineers, working on fundamental research problems and collaborating with Datadog's product and engineering teams to translate research advances into products. Building on our track record of AI-powered solutions (e.g., Bits AI , Bits Evolve , and our time series foundation model ), Datadog AI Research tackles high-risk, high-reward problems grounded in real-world challenges in cloud observability and security. We are focused on two research areas: World Models for Observability -- Training multimodal foundation models that learn the joint dynamics of distributed systems across metrics, traces, logs, topology, and events. These models power advanced forecasting, anomaly detection, root cause analysis, counterfactual simulation ("what if?"), and provide a learned planning backbone for our autonomous agents. Trained Agents for Observability -- Post-training models to operate autonomously across Datadog's domain. SRE incident response is our first target, with a clear path to code repair, security response, and infrastructure optimization. We build the simulation environments, RL training loops, and evaluation infrastructure needed to train agents that match or surpass frontier models at a fraction of the cost. What You'll Do: Conduct research in generative AI and machine learning, building specialized foundation models and trained agents for observability Train multimodal models on large-scale, diverse telemetry data (metrics, logs, traces, topology, events) using distributed training infrastructure Design and build simulated environments and RL training loops for on-policy agent training and evaluation Collaborate with cross-functional teams (Product, Engineering) to integrate capabilities like multimodal world modeling and autonomous agents into Datadog's products Stay at the forefront of foundation models, world models, and RL-based agent research Contribute to r

Associate Software Engineer Company: The Boeing Company The Boeing Company has an exciting opportunity for an Associate Software Engineer to support the ADaPS organization in Huntsville, AL. ADaPS (an organization of over 100 software engineers) supports programs across the entire portfolio of Boeing products including Space Launch Systems (SLS), Satellite Efforts, and Advanced Missile Defense efforts including Patriot Advanced Capability (PAC3) and Integrated Fires Protection Capability 2nd Interceptor (IFPC – 2). ADaPS specializes in implementing rapid prototyping and development programs using small, adaptable agile teams. Position Responsibilities: Assists with the development and fielding of flight software for seeker systems Assists with the design and development of test software for seeker software Assists with the development and integration of Weapons Open System Architecture Framework Domains into missile and weapons systems Assists with the development firmware and its integration with hardware/software Works in small agile teams composed of diverse engineering skills Use your talents to tackle complex problems on a variety of programs Develops technical products, plans, documentation, and briefings in support of program requirements Assists with review, analysis and translation of customer requirements into initial design of software products Supports development, documentation and maintenance of architectures, requirements, algorithms, interfaces and designs for software products Security Clearance: This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires

Job Details: Job Description: The Thin Films Senior Process Engineer will support PVD, CVD, and ALD technologies for dielectric and metal thin-film deposition in a high-volume manufacturing environment. Key Responsibilities Apply advanced expertise in thin-film deposition processes to drive continuous improvement in process performance, sustainment, and technology development. Collaborate with upstream and downstream partners to deliver manufacturing improvements through strong cross-functional engagement and stakeholder management. Own manufacturing processes and/or equipment, ensuring achievement of key performance indicators (KPIs) including safety, quality, cost, productivity, defect reduction, and yield improvement. Develop and execute strategic plans for complex projects, coordinating timelines and dependencies across multiple teams and initiatives. Support manufacturing capacity expansion and technology transfer activities to enable successful ramp-to-volume production. Partner with equipment vendors and cross-functional stakeholders to troubleshoot technical challenges, improve tool performance, and enhance operational efficiency. Lead process development initiatives that support current and next-generation high-volume manufacturing technologies. Design and optimize excursion prevention and detection systems to strengthen process control and minimize manufacturing risk. Lead equipment installation, conversion, qualification, and readiness activities during factory ramps, ensuring all tools are deployed safely, on schedule, and in compliance with quality and manufacturing standards. Drive root cause analysis and implement corrective actions to resolve process and equipment-related issues while improving overall manufacturing stability and performance. <p st

About the Team The Core Network Engineering team owns the end-to-end networking stack that connects OpenAI’s compute infrastructure — spanning global WAN/edge connectivity, data-center networking, and high-performance host/xPU networking used for large-scale training and inference workloads. This team is responsible for ensuring networking is never the bottleneck to model training efficiency, cluster reliability, or fleet expansion. They design and operate the systems that provide predictable, high-throughput, low-latency connectivity across some of the world’s most advanced AI infrastructure. About the Role We’re looking for engineers to help build and operate the networking foundation behind OpenAI’s frontier AI systems. Depending on your background and area of focus, you may work across host networking, datacenter fabrics, or global WAN infrastructure. The problems span low-level systems software, distributed infrastructure, protocol readiness, observability, performance engineering, automation, and large-scale network operations. You’ll work on systems where microseconds of latency, tail performance, and network reliability directly impact model training efficiency and production serving performance. This role is ideal for engineers who enjoy operating close to the hardware/software boundary and solving performance-critical infrastructure problems at massive scale. In this role, you will: Design, build, and operate networking systems that support large-scale AI training and inference infrastructure Improve performance, reliability, and scalability across host networking, datacenter fabrics, and WAN systems Develop automation for provisioning, configuration management, validation, upgrades, and lifecycle management of networking infrastructure Build tooling and observability systems for network health, performance analysis, debugging, and automated remediation Optimize network performance across technologies such as RDMA, RoCE, InfiniBand, Ethernet, and high-perf