Ai And Cloud Service Provider Account Executive in United States

ABOUT BASETEN Baseten powers mission-critical inference for the world's most dynamic AI companies, like Cursor, Notion, OpenEvidence, Abridge, Clay, Gamma and Writer. By uniting applied AI research, flexible infrastructure, and seamless developer tooling, we enable companies operating at the frontier of AI to bring cutting-edge models into production. We're growing quickly and recently raised our $1.5B Series F , led by Altimeter Capital, Conviction Partners, and Spark Capital. Join us and help build the platform engineers turn to to ship AI products. THE ROLE As a Product Engineer on the Dedicated Inference team, you'll shape the state-of-the-art developer experience for deploying and operating AI workloads in production. From the CLI and SDKs to APIs, observability, and debugging workflows, you'll build the tools customers rely on every day to manage mission-critical inference deployments. Few teams at Baseten have as much breadth and visibility as Dedicated Inference. The team is often at the forefront of new product development, giving engineers the opportunity to shape the experience of some of our most important customers. EXAMPLE INITIATIVES You'll get to work on these types of projects as part of our Dedicated Inference team: Chains for multi-component workflows Asynchronous inference Model APIs for frontier models Model training built for production inference RESPONSIBILITIES Implement new features and products for the team Design ergonomic APIs and abstractions to solve customer problems Fix bugs and resolve customer issues with urgency Work across the stack - regardless of where you start, you’ll end up touching both React Components and Kubernetes Pods Work closely with the product and forward deployed engineering teams to develop and drive new product ideas REQUIREMENTS Bachelor's degree or higher in Computer Science or related field Proficient coding abilities in one or more popular programming or scripting languages; Python, Go, or Javascript proficie

ABOUT BASETEN Baseten powers mission-critical inference for the world's most dynamic AI companies, like Cursor, Notion, OpenEvidence, Abridge, Clay, Gamma and Writer. By uniting applied AI research, flexible infrastructure, and seamless developer tooling, we enable companies operating at the frontier of AI to bring cutting-edge models into production. We're growing quickly and recently raised our $1.5B Series F , led by Altimeter Capital, Conviction Partners, and Spark Capital. Join us and help build the platform engineers turn to to ship AI products. THE ROLE We’re looking for a seasoned Frontend Engineer to craft performant and delightful user experiences across Baseten’s core platform. You’ll own critical parts of our web application stack and collaborate cross-functionally with product, design, and backend teams to launch impactful features that help users deploy and manage AI systems at scale. EXAMPLE INITIATIVES You'll get to work on these types of projects as part of our Core Product team: Rolling Deployments Model APIs for frontier models Model training built for production inference RESPONSIBILITIES Design, implement, and maintain responsive, accessible, and user-friendly frontend interfaces using React and TypeScript Collaborate closely with product designers to turn complex ideas into elegant, intuitive UIs Optimize application performance and reliability, with a focus on rendering speed and responsiveness Drive major frontend initiatives, including partnering with backend teams to define APIs and test and refine end-to-end flows Establish best practices, and mentor other engineers on frontend technologies Build reusable component libraries and frontend infrastructure that accelerate product development Partner with backend and platform teams to define and refine APIs and end-to-end flows REQUIREMENTS 5+ years of experience building production-grade web applications Deep expertise in React, TypeScript, and modern web development tooling Track record of bu

Replit is the agentic software creation platform that enables anyone to build applications using natural language. With millions of users worldwide, Replit is democratizing software development by removing traditional barriers to application creation. As a GTM & G+A Sourcer , you won't just be filling seats; you will be the primary architect of the talent pipeline that builds the future of our business, operations, and growth teams. We are seeking a Fixed Term Full Time employee for a 6 - 12 month term . The Mission At Replit, we don’t look for average talent; we look for "10x" builders and creators. Your mission is to find the needles in the haystack—high-impact professionals across Go-to-Market (Sales, Marketing, Growth) and G+A (Finance, People, Ops) who are product-minded and excited by the challenge of democratizing coding. Key Responsibilities Strategic Pipeline Building: Identify and engage top-tier talent for GTM functions and G+A roles. Creative Outreach: Utilize AI tools to streamline workflows while crafting highly personalized, compelling outreach that resonates with the Replit ethos. Deep Research: Map out talent across LinkedIn, X (Twitter), competitive startups, and niche professional communities to uncover "undiscovered" talent. Full Lifecycle Partnership: Collaborate closely with Recruiters and Business Leads to calibrate profiles and refine search strategies in real-time. Data-Driven Iteration: Track conversion rates and leverage data to pivot sourcing strategies as needed. Who You Are Experience: 3+ years of sourcing experience with a focus on GTM or G+A roles, ideally within a high-growth startup environment. Business Acumen: You understand the AI/SaaS landscape and know what excellence looks like in non-technical candidates within our specific culture. Persistence: You possess a "hunter" mentality and enjoy the challenge of identifying talent for highly specific, specialized roles. High Agency: You are self-directed, comfortable operating wi

This is a senior individual contributor role for someone who wants to actively shape how Engineering, one of the most important parts of how Datadog develops its people. You'll sit at the center of Datadog's biggest talent bets for Engineering: how we build leaders, define career paths and org design, evolve performance, move talent internally, and plan succession for our most critical roles. You’ll own this work end to end, from the first framing conversation with senior leaders through to delivering a program running at scale. AI is changing how Engineering builds software, and it is changing how People builds the programs that support Engineering too. This role sits at the centre of both: understanding how AI is reshaping engineering roles, skills and structures, and building AI-powered solutions within People to keep pace. At Datadog, we place value in our office culture - the relationships and collaboration it builds and the creativity it brings to the table. We operate as a hybrid workplace to ensure our Datadogs can create a work-life harmony that best fits them. What You’ll Do: Design and lead complex talent programmes for Engineering, spanning leadership capability, career architecture, org design, performance, internal mobility and succession for critical roles. Partner directly with PBPs and senior leaders to turn ambiguous problems into clear programme goals, design principles and success measures. Help Engineering and People understand and respond to how AI is reshaping roles, skills and ways of working, and translate that shift into practical talent and org design choices. Stay hands-on from concept through to adoption: this is a build and run role, not a strategy and handover role. Work across Enablement, Learning, People Analytics and People Systems so what you build scales and embeds into core people processes. Equip PBPs with frameworks, tools and executive-ready narratives that support real adoption in the business. Operate in ambigu

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for a software engineer to help build the design methodology, software abstractions, and infrastructure that enable a small silicon team to develop complex chips rapidly and with high confidence. You will turn evolving architecture and design needs into reusable tools and workflows that improve iteration speed, quality, and then apply those tools to help construct world-class silicon. You’ll work closely across architecture, design, verification, performance modeling, and systems software. This role is well suited for an engineer who enjoys building high quality software and is motivated by the challenge of improving velocity and quality of the silicon development process. In this role, you will: Develop and scale design methodologies for rapid first-party chip development and apply them to construct complex custom chips Create abstractions that allow hardware structures, configurations, experiments, and results to be represented consistently across tools. Automate high-value engineering workflows and improve their reproducibility, observability, testability, and ease of use. Partner with architects, RTL designers, verification engineers, compiler engineers, and systems software engineers to gather requirements and then implement solutions. Use methodology and tooling to identify design risks early, accelerate iteration, and improve confidence in performance and implementation tradeoffs. Contribute across multiple aspects of software and hardware

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for an experienced systems software engineer to help define and build the host software stack for our custom next-generation AI systems. You will work close to the hardware on performance-critical software, including Linux kernel drivers, high-throughput I/O paths, and system-scale networking and RDMA. This role spans architecture, implementation, platform bring-up, debugging, and performance optimization. You will work across hardware and software boundaries to make new systems usable end to end, from low-level device interfaces through userspace tooling and production validation. In this role you will: Design, implement, and debug host-side systems software for AI infrastructure, including Linux kernel drivers and supporting userspace components. Build and optimize software paths for high-throughput, low-latency communication, including RDMA and related networking functionality. Develop software around PCIe, DMA, NICs, accelerators, memory movement, and device interaction. Bring up new hardware platforms and diagnose complex issues across kernel, firmware, networking, and hardware boundaries. Build tooling for integration, testing, diagnostics, observability, qualification, and performance characterization. Collaborate with hardware, networking, and platform teams to define interfaces and integrate new capabilities. Work with external vendors where needed to integrate technologies and drive issues to resolution. Contribute across the systems sof

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale. This is a senior, hands-on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure, physical design convergence, bring-up, and production readiness. You will plan and oversee the work of junior engineers and help drive and develop productive engineering relationships with external partners and help manage partner execution. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic as well as off-chip protocol bridges and interfaces. Drive third party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and de

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We're seeking a Security Engineer to join our First-Party Hardware team. In this role, you will own the end-to-end security foundation for OpenAI's first-party AI hardware systems, working across hardware security, embedded security, system security, and practical deployment at data center scale. You will partner with silicon, hardware, firmware, infrastructure, manufacturing, operations, and security teams to define and deliver system-level device trust. This includes boot integrity, device identity, provisioning, attestation, management-plane security, storage encryption, debug controls, firmware update and recovery, RMA, and decommissioning. You will be accountable for turning threat models into requirements, requirements into implementation, and implementation into validation evidence that can support launch decisions. Location: San Francisco, CA (Hybrid: 3 days/week onsite) Relocation assistance available. In this role, you will: Own security requirements, threat models, validation strategy, and launch-readiness evidence for first-party hardware platforms from early design through production deployment. Design and review secure boot, measured boot, roots of trust, platform firmware resilience, firmware signing, recovery, and anti-rollback strategies across heterogeneous devices. Own device identity, provisioning, enrollment, attestation, certificate lifecycle, and key-management requirements across manufacturing and data center bring-up. Harden management

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are seeking a Technical Lead to lead deployment and operations for OpenAI’s Silicon & Systems team. This person will become the Directly-Responsible Individual responsible for bringing OpenAI’s custom silicon and associated systems into data center environments, ensuring successful deployment, bring-up, validation, operational readiness, and ongoing reliability at scale. This role sits at the intersection of silicon, systems, infrastructure, data center operations, and software. You will lead a team focused on taking new hardware platforms from lab validation into production data center deployment. You will be responsible for building the operational processes, technical workflows, tooling, and cross-functional alignment required to deploy and operate custom AI hardware reliably in OpenAI’s supercomputing infrastructure. The ideal candidate is both a strong leader and a deeply technical operator. You should be comfortable staying close to the technical details of hardware bring-up, fleet deployment, debugging, system validation, data center integration, and production operations. This role requires strong execution, excellent cross-functional judgment, and the ability to drive clarity in ambiguous, fast-moving environments. In this role, you will: Lead a team responsible for deployment and operations of OpenAI’s custom silicon and systems in data center environments Own the path from hardware bring-up and validation through production deployment, operati

About the Team OpenAI Finance ensures the organization’s financial integrity and scalability in pursuit of our mission. Our Financial Reporting team is central to delivering accurate, timely, and GAAP-compliant financial information to internal and external stakeholders. We focus on building robust, scalable reporting systems and processes to support rapid organizational growth and complexity. About the Role OpenAI is hiring a Senior Manager, Financial Reporting to help build and run a best-in-class financial reporting engine in a technically complex, rapidly evolving, and high-growth environment. We are looking for a seasoned external reporting professional who pairs strong technical judgment with a roll-up-your-sleeves mindset - owning key reporting deliverables, driving rigorous tie-outs and disclosure quality, and converting ambiguity into audit-ready output. This role will collaborate closely with teams across Accounting, FP&A, Tax, Legal, and Investor Relations to improve reporting processes, streamline data flows, and elevate how financial information is communicated across stakeholders. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Modernize reporting workflows through AI integration — Leverage ChatGPT, Codex, and proprietary AI tools to minimize manual effort and accelerate deep analysis, while maintaining the rigorous judgment and accountability required for high-quality, audit-ready outputs. Own end-to-end financial statements and disclosures — Prepare GAAP financial statements, footnotes, and supporting schedules; maintain rollforwards, tie-outs, and internal consistency checks to ensure outputs are complete and audit-ready. Drive audit readiness and execution — Partner with external auditors to manage day-to-day audit workflow (PBC coordination, support quality, issue resolution) and keep reporting on track with minimal re

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role As a software engineer on the Scaling team, you’ll help build and optimize the low-level stack that orchestrates computation and data movement across OpenAI’s supercomputing clusters. Your work will involve designing high-performance runtimes, building custom kernels, contributing to compiler infrastructure, and developing scalable simulation systems to validate and optimize distributed training workloads. You will work at the intersection of systems programming, ML infrastructure, and high-performance computing, helping to create both ergonomic developer APIs and highly efficient runtime systems. This means balancing ease of use and introspection with the need for stability and performance on our evolving hardware fleet. This role is based in San Francisco, CA, with a hybrid work model (3 days/week in-office). Relocation assistance is available. In this role, you will: Design and build APIs and runtime components to orchestrate computation and data movement across heterogeneous ML workloads. Contribute to compiler infrastructure, including the development of optimizations and compiler passes to support evolving hardware. Engineer and optimize compute and data kernels, ensuring correctness, high performance, and portability across simulation and production environments. Profile and optimize system bottlenecks, especially around I/O, memory hierarchy, and interconnects, at both local and distributed scales. Develop simulation infrastructure to validate runtime b

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role You will develop and evolve the tooling ecosystem that hardware engineers rely on every day — from hardware compilers and IR transformations to simulation, debugging, and automation infrastructure. The work spans software engineering, compiler concepts, and practical hardware workflows, with direct impact on how quickly and effectively we design next-generation AI systems. You’ll collaborate closely with architects, RTL designers, and verification engineers to translate real engineering friction into durable, scalable tooling solutions. In this role you will: Build and improve the software tooling that makes hardware teams faster: compilation, IR transforms, RTL generation, simulation, debug, and automation. Extend and integrate hardware compiler stacks (frontends, IR passes, lowering, scheduling, codegen to Verilog/SystemVerilog) and connect them to real design workflows. Improve developer experience and reliability: reproducible builds, better error messages, faster iteration loops, and dependable CI and regression infrastructure. Work closely with designers and verification engineers to turn real pain points into durable tools. Dive into RTL when needed: read and reason about Verilog/SystemVerilog to debug issues, validate tool output, and improve debuggability. Be willing to go all the way down the stack when necessary, including gate-level views, synthesis results, and implementation artifacts. Help enable PPA optimization loops by building analysis and au

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for an embedded engineer to help build firmware and associated modeling software for OpenAI’s in house AI accelerator. This role involves designing and developing drivers and functional models for a large array of HW components, writing high throughput and low latency firmware code, investigating bring-up and production issues. Responsibilities Design and implement drivers for hardware peripherals, including those related to AI chips. Design and implement functional software models to simulate SoC uncore logic and enable FW testing against the model Design and implement low-latency and high throughput embedded SW to manage HW resources. Work with adjacent software and hardware teams to implement requirements, debug issues and shape future generations of the hardware. Collaborate with vendors to integrate their technologies within our systems. Bring up and debug firmware/driver on new platforms. Come up with processes and debug issues raised in the field. Set up monitoring, integration testing and diagnostics tools. Qualifications 5+ years of experience working in embedded SW space. Ability to thrive in ambiguity and learn new technologies. Strong programming skills in C/C++ and/or Rust. Experience developing high throughput, low latency and multi-threaded code. Experience working with real time operating systems (RTOS). Experience developing hardware drivers and working with hardware Experience with HW/SW co-design Knowledge of common embedded pr

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for signal integrity (SI) system design engineers who have a deep expertise in the SI area, and hold strong system level design knowledge This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Lead system signal integrity (SI) design for AI supercomputer product in the data center application. Collaborate with chip, package, boards, rack and system engineers, design partners to drive system SI design and develop innovative interconnect and high-speed technologies Identify and evaluate new technologies and methodologies to improve signal and power integrity in product design, and contribute to the development of new products and technology by providing expertise in signal integrity Perform simulation and modeling to identify and troubleshoot signal integrity issues Lead system interconnect design, bring up and qualification As the scope of the role and team grows, understand and influence roadmaps for hardware partners for our datacenter networks, racks, and buildings. You might thrive in this role if you: Have at least 10 years of industry experience, including experience design hardware system and SerDes testing for data center applications Have a strong bias toward action, and won’t take no for an answer. Have experience and good knowledge of system design experience in the SI areas, from chip, SerDes, board, rack level Have ex

About the Team: OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale. In this role you will: Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality. Define verification plans based on architecture and microarchitecture specs. Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies. Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness. Drive bug triage, root cause analysis, and work closely with design teams on resolution. Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments. You might thrive in this role if you have: BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification. Proven success verifying complex IP or SoC designs in industry-standard flows Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi). Strong knowledge