Cpu Floorplan Lead in United States

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an exceptional Senior-level Physical Design Engineer to drive top-level implementation of our complex AI and CPU System-on-Chip designs. You'll orchestrate cross-disciplinary collaboration, implementing sophisticated floorplans, power grids, and clock networks while ensuring design closure at the chip level. If you excel at managing the complexity of full-chip physical design and want to deliver next-generation AI hardware, we need your expertise. This role is hybrid , based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned physical design engineer who thrives on complex, full-chip implementation challenges. Expert at collaborating across disciplines, working effectively with architecture, RTL, and packaging teams. Passionate about optimizing chip-level implementations for power, performance, and area. Detail-oriented professional who drives design closure while maintaining quality and meeting aggressive schedules. What We Need 8+ years of top-level SOC physical design experience on complex, multi-million gate designs. Deep expertise in hierarchic

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we build open, state of the art compute for real workloads and real developers. You will own CPU core-level testbench development and verification, shaping how our out-of-order RISC-V CPUs behave in silicon. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring 8+ years in CPU verification, CPU testbench development, or closely related digital design. You have deep hands-on experience building and owning CPU core-level testbenches, not just using existing environments. You know high-performance out-of-order CPU microarchitecture in depth. You are comfortable developing testbench infrastructure in CVM methodology, with UVM experience as a strong plus. You work comfortably across RTL, waveforms, logs, regressions, and cross-functional debug with design, DV, emulation, and post-silicon teams. You are comfortable using AI-assisted verification workflows to improve debug, stimulus creation, and coverage analysis, while applying strong engineering judgment to validate results. What We Need Lead hands-on CPU core-level testbench development for hi

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we build open, state of the art compute for real workloads and real developers. You will own CPU focused test generator development and verification strategy, shaping how our out-of-order RISC-V CPUs are validated against complex ISA and microarchitectural behavior. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring 8+ years in CPU design verification, test generation, or closely related CPU validation work. You have led development of test generators for x86, ARM, or RISC-V ISA environments. You understand CPU ISA behavior, privileged architecture, and high-performance out-of-order CPU microarchitecture. You are comfortable building tools, stimulus, and automation that scale verification across large CPU programs. You communicate clearly across design, DV, architecture, emulation, and post-silicon teams. What We Need Lead development of CPU core-level test generators for high-performance out-of-order RISC-V cores. Own generator strategy, infrastructure, and methodology for ISA and microarchitectural verification in both pre-silico

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a CPU Verification Fellow to lead verification strategy and execution for next-generation RISC-V high-performance processors. This role requires deep CPU verification expertise, strong microarchitecture understanding, and the ability to guide large engineering teams from early design through tapeout and post-silicon validation. The ideal candidate has verified complex out-of-order, speculative, superscalar CPUs and can define scalable methodology across simulation, formal verification, emulation, FPGA, and silicon bring-up. This role is hybrid, based out of Santa Clara, CA or Austin, TX. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You have deep experience verifying high-performance superscalar CPUs, ideally including out-of-order and speculative processors. You have strong knowledge of RISC-V architecture, including ISA compliance, privileged architecture, virtual memory, atomics, vector extensions, and memory model behavior. You are highly proficient in SystemVerilog, UVM, constrained-random verification, assertions, functional coverage, and advanced debug methodologies. You have hands-on experience with CPU refere

About the Team OpenAI’s Infrastructure organization builds the systems that power frontier AI workloads at global scale. As compute demand accelerates, our ability to rapidly convert infrastructure investments into usable production capacity has become mission critical. The CPU / Storage / PoP / WAN team is responsible for the end-to-end infrastructure layers required to bring compute online: server and cluster activation, storage platforms, Points of Presence (PoPs), backbone connectivity, and global network expansion. We operate across first-party facilities, colocation environments, and strategic cloud partners to ensure OpenAI can scale reliably and quickly. About the Role We are seeking a highly technical Program Manager to lead execution across CPU, Storage, PoP, and WAN infrastructure programs that directly unlock OpenAI’s next generation compute capacity. In this role, you will own complex cross-functional programs spanning compute cluster activation, storage deployment, PoP bring-up, and backbone expansion. You will coordinate hardware readiness, site readiness, network pathing, storage availability, vendor execution, and engineering dependencies required to turn contracted infrastructure into live training and inference capacity. This role requires strong technical fluency across hardware systems, network infrastructure, storage architecture, and deployment execution. You should be comfortable operating from rack-level implementation details through executive-level capacity planning discussions. This role is based in San Francisco, CA, with travel as needed. Key Responsibilities Lead end-to-end execution of CPU / GPU cluster activation programs across OpenAI’s global infrastructure footprint Drive readiness to convert contracted compute capacity into schedulable production clusters Own deployment programs for new PoPs, backbone nodes, WAN expansion, and interconnection initiatives Build integrated schedules spanning procurement, logistics, installation, st

About the Team The Stargate team is responsible for building the physical infrastructure that powers large-scale AI systems. We design and deliver next-generation data centers optimized for dense compute clusters, advanced networking, and rapidly evolving hardware platforms. This work sits at the intersection of hardware engineering, systems architecture, and infrastructure execution—translating cutting-edge compute roadmaps into scalable, production-ready environments. Our teams partner across silicon vendors, server and storage OEMs, networking teams, and data center engineering organizations to bring new capacity online quickly, reliably, and at global scale. About the Role We are seeking a CPU & Storage Technical Lead to define and drive the server compute and storage architecture strategy for Stargate infrastructure. In this role, you will own technical direction across CPU platforms, memory configurations, local and disaggregated storage systems, and their integration into large-scale AI clusters. You will evaluate vendor roadmaps, lead platform tradeoff decisions, and ensure compute and storage systems are optimized for training, inference, and supporting services. You will work cross-functionally with hardware engineering, performance modeling, networking, supply chain, and deployment teams, as well as external partners such as AMD, Intel, OEMs, ODMs, and storage vendors. This is a highly strategic role for someone who can operate deeply at the component level while also driving long-range infrastructure decisions. Key Responsibilities Own CPU and storage technical strategy for Stargate compute infrastructure across current and future generations. Evaluate CPU platforms across performance, efficiency, memory bandwidth, PCIe topology, cost, and roadmap alignment. Define storage architectures for AI environments, including boot media, local NVMe, shared storage, caching tiers, metadata services, and high-performance data pipelines. Drive server platform de

Job Details: Job Description: Do Something Wonderful At Intel, we put silicon at the center of the world’s most meaningful innovations. From personal computing and AI to cloud-scale data centers and edge platforms, our processors power technologies that touch billions of lives. If you’re passionate about building world-class silicon at massive scale, we want to build the future with you. The Team You’ll join Intel’s All Cores Engineering (ACE) organization, the team responsible for designing and delivering Intel’s industry‑leading CPU cores. Within ACE, the Atom group focuses on high‑efficiency, performance‑per‑watt optimized cores that enable everything from client platforms to emerging edge and scalable solutions. This is a hands‑on senior engineering role with direct impact on next‑generation CPU silicon. What You’ll Do As a Senior CPU Design Verification Engineer you will play a critical role in ensuring architectural correctness, functional robustness, and power‑efficient performance of Intel’s Atom CPU designs before first silicon. Key responsibilities include but not limited to the following: Lead pre‑silicon functional verification of complex CPU and SoC logic to ensure full compliance with architectural and microarchitectural specifications. Develop and execute verification plans, testbenches, and SystemVerilog/UVM environments, ensuring comprehensive functional and coverage closure. Define, run, and analyze system‑level simulations to uncover functional, performance, power, and corner‑case issues. Debug and root‑cause complex RTL, microarchitecture, and integration issues; drive issues to resolution with design teams. Collaborate cross‑functionally with CPU architects, RTL de

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Our Tensix Team is building the future of AI compute with a ground-up architecture centered on scalable RISC-V processors. As we push performance boundaries, we’re reimagining the frontend of our RISC-V cores to deliver major gains in programmability, efficiency, and developer experience. This is a rare opportunity to shape the CPU architecture at the heart of our AI platform and lead one of the most strategic technical efforts at Tenstorrent. This role is hybrid, based out of Toronto, ON, Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experienced Microarchitect: 10+ years of deep expertise in CPU performance modeling and microarchitecture design. AI Workload Expert: Deeply familiar with the computational and memory bottlenecks of modern AI workloads, particularly Large Language Models (LLMs). Hardware-Software Co-Designer: Driven to architect custom instruction set extensions and validate their performance gains against real-world workloads. Ways to stand-out: Familiarity with open-source RISC-V cores, AI-based agentic workflow experience What We Need Profile & Analyze: Dissect cutting-edge AI workloads to identi

We are looking for a disciplined and dynamic, Lead System Engineer – compute blade and rack Validation to join our growing compute rack validation team. As a diligent leader in Systems Engineering, you will drive multiple aspects of validation throughout the life cycle of the program. In this high visibility position, you will be part of a leading team to innovate and improve system bring-up and enablement abilities, as well as silicon and system validation to deliver the highest quality, industry leading technologies to market. Your technical leadership skills, validation and debug expertise will be necessary towards product development, definition, root cause and resolution. Your agility and collaborative approach will be essential to work within System Validation & other engineering teams (System Architects, SoC and Rack FW etc). The technical leader will be driving keys areas of system validation including leading first silicon & system bring-up (nodes and rack level systems) - rack level systems and blades will be based of ARM server architecture. Candidate will be immersed in challenging system enablement work, system validation (end-to-end) methodology, tests development and execution as well as triage/debug of critical issues to meet critical program milestones at POR quality. The candidate will also be a key contributor to state-of-the-art HW and lab capabilities for Grapchore’s system engineering. The candidate should be able to work in a global environment while maintaining a synergetic culture. Primary Responsibilities: Lead the systemenablement (including first silicon and other FW components) to ensure system capabilities are brought up as per plan of record and system architecture spec. Drive organization wide methodology for Firmware integration and best known configuration (HW/FW/SW) usage model by leading the release of deployment ready solutions. Develop key methodologies, lab HW and system SW capabilit

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team to define and implement RTL for high-performance CPUs. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experienced in CPU microarchitecture with expertise in Rename, Scheduler, ROB, Load Store, Branch Prediction, Cache or Datapath. Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis. Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments. Background in microarchitecture definition, design specification, and performance-driven trade-off analysis. What We Need Own RTL design and microarchitecture development for a portion of a CPU block of a high-performance RISC-V CPU. Collaborate closely with DV, PD, and performance engineers to meet functional, timing, and power goals. Use innovative techniques to optimize power, performance, and

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a Design Verification Engineer to contribute to the unit-level verification of our RISC-V CPU front end—including instruction fetch, branch prediction, and surrounding fetch control structures. As a key individual contributor within our front-end DV team, you will focus on building testbenches, generating stimulus, and developing checkers for complex microarchitectural scenarios. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Front-End Experience: Solid background verifying CPU front-end blocks—such as instruction fetch, branch predictors (BTB, TAGE, RAS), instruction caches/TLBs, or decode—using SystemVerilog, UVM, and C++. Unit-Level Focus: Hands-on experience building clean, controllable unit testbench environments with precise stimulus and checking. Reusable Design: Pragmatic approach to building transactors, predictors, and scoreboards that can be reused across verification levels. Collaborative Problem Solver: Comfortable working alongside RTL designers to trace and fix misspeculation, redirect, and edge-case fetch bugs. What We Need Unit-Level Verifica

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is building next-generation processors and systems, bringing together world-class expertise across silicon, systems, and software. We are looking for a CPU Performance Modeling Architect to help evaluate, shape, and optimize the performance of future CPU architectures. In this role, you’ll use performance modeling, workload analysis, and deep understanding of CPU architecture to answer complex questions about how a processor should be designed. You’ll work closely with CPU architects, RTL designers, software and compiler teams, and system engineers to identify performance opportunities, evaluate architectural tradeoffs, and turn modeling insights into actionable design decisions. This role is hybrid, based out of Santa Clara, CA or Austin, TX. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A CPU architect, performance architect, or performance modeling engineer with experience influencing CPU architecture or microarchitecture decisions. You have a strong understanding of modern processor architecture and enjoy digging into why a CPU performs the way it does. You are comfortable combining hardware architecture, software, data, and

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an experienced Field Application Engineer to champion our revolutionary RISC-V CPU and AI accelerator IP products with customers worldwide. You will own end-to-end technical engagements, translating complex architectural advantages into customer wins while shaping our product roadmap through direct market feedback. If you combine deep technical expertise with exceptional customer engagement skills and want to drive the adoption of next-generation compute IP, join our team. This role is hybrid, based out of the United States or Canada near one of our main office locations. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A customer-focused engineer with proven success in CPU/GPU/NPU IP sales engagements. Technical expert who can articulate complex architectural benefits and conduct deep-dive analyses. Self-driven professional who independently manages multiple customer relationships from discovery to win. Strategic thinker who identifies customer pain points and positions solutions effectively. What We Need 7+ years in the semiconductor industry with a degree in EE or related field including customer-facing roles i

Job Details: Job Description: About the Role Join a team developing next-generation CPU cores that power client, server, IoT, and AI platforms. As a Senior Physical Design Engineer (CPU), you will play a key role in delivering high-performance, power-efficient silicon solutions. You will take ownership of blocks within the CPU core design, driving implementation from RTL to GDS and contributing to advanced physical design methodologies. What You’ll Do Key responsibilities will include but not limited to: Own physical design and implementation of CPU core blocks or subsystems Execute synthesis, floorplanning, place and route, and design closure Perform static timing analysis (STA), power analysis, and physical verification Drive convergence of timing, power, and area (PPA) metrics Debug and resolve complex design issues across multiple design stages Develop and optimize design flows and automation scripts Collaborate cross-functionally with RTL design, verification, clocking, and full-chip teams Contribute to improving design methodologies and best practices Provide guidance to junior engineers where applicable Behavioral traits that we are looking for: Strong problem-solving and analytical thinking Takes ownership and accountability for deliverables Collaborates effectively across multidisciplinary teams Communicates technical concepts clearly and concisely Prioritizes work effectively in a fast-paced environment Continuously learns and applies new tools and methodologies Why Join Us Work on cutting-edge CPU core designs that power client, server, IoT, and AI platforms used worldwide Be part of

NVIDIA’s Silicon Co-Design Group is the team that gets every GPU, SoC, and CPU silicon program from first power-on to high-volume production. We are hiring a Senior Manager to lead our Test, Manufacturability, Reliability & Quality (TMRQ) organization. This is not a coordination role . Your work decides if a product can be built at scale and trusted in the field. These include production test development (SLT, BLT), control run flow, system reliability stress (HTOL), platform- and board-level manufacturing issue closure, and field diagnostic test development. You lead a team of individual contributors and a first-line manager at the layer where silicon, platform, and software collide with manufacturing reality. Decisions you make show up in yield curves, production ramp , and customer escapes. You are the leader the program turns to when a build is stuck, a control run is fallout-heavy, or a field return points back at silicon . The exceptional hire also uses AI deliberately — with demonstrated workflow impact and the judgment to know where it compresses real work and where it introduces risk. What you will be doing: Keep programs moving. Own the technical execution and velocity of SLT, BLT, Board/Chip/Rack CR, and system reliability stress (HTOL) across every GPU, SoC, and CPU silicon program. Close the hardest multi-functional failures. Resolve Vmin and binning escapes, performance shortfalls, and power anomalies by driving root-cause across design, methodology, DFT, ATE, package, software/firmware, and manufacturing — and own the WARs and productized fixes through to confirmation. Give leadership the clarity to act. Convert raw integration signals — CR fallout, BLT/SLT yield, SHTOL/CHTOL data, RMA trends, customer escalations — into decision-ready options that enable executive leadership to act with confidence on POR, QS/PS gates, a