Design Quality Engineer in United States

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. NVIDIA is seeking best-in-class ASIC Verification Engineers to verify the design and implementation of the world’s leading inference accelerator. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people around the globe. Their mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will help to build the high-performance processor elements that implement programmable compute and graphics functionality. What you'll be doing: As a key member of our ASIC Verification team, you will verify the design and implementation of inference accelerator You will be responsible for verification of the ASIC design, architecture, reference models and micro-architecture using advanced verification methodologies Understand the design and implementation of your unit, define the verification scope, develop the verification infrastructure and verify the correctness of the design Collaborate with architects, designers, and pre and post silicon verifi

What if the work you did every day could impact the lives of people you know? Or all of humanity? At Illumina, we are expanding access to genomic technology to realize health equity for billions of people around the world. Our efforts enable life-changing discoveries that are transforming human health through the early detection and diagnosis of diseases and new treatment options for patients. Working at Illumina means being part of something bigger than yourself. Every person, in every role, has the opportunity to make a difference. Surrounded by extraordinary people, inspiring leaders, and world changing projects, you will do more and become more than you ever thought possible. Responsibilities: Drive staff results by communicating job expectations, planning, monitoring and appraising job results, coaching and counseling employees, recognizing performance issues and driving improvement, developing, coordinating and enforcing systems, policies, procedures and productivity standards Establish strategic goals by gathering pertinent business, financial, service and operations information, choosing a course of action, defining objectives, and evaluating outcomes Maintain staff by recruiting, selecting, orienting and training employees; maintaining a safe, secure and legal work environment; developing personal growth opportunities Ensure validation program meets requirements of FDA (21 CFR Part 11 and Part 820), ISO 9001/13485, IEC 62304 and MDSAP Identify differences between ISO and FDA requirements and their applicability to products targeting different markets Report broadly through the organization on validation activities and instrument manufacturing audit readiness Estimate timelines and budgeting for validation engineering development efforts Formaliz

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our team is at the forefront of developing next-generation memory and AI computing platforms. We are core contributors to the design, validation, and mass production of advanced systems using emerging memory technologies, ASICs, FPGAs, high-speed digital interfaces, mixed-signal and analog circuitry, and complex power delivery architectures! We are seeking a highly experienced Mechanical & Thermal Engineer to provide technical leadership and drive the mechanical and thermal architecture of ground breaking hardware platforms. This role offers the opportunity to influence product strategy, lead critical engineering decisions, and collaborate across global multidisciplinary teams to enable world-class computing solutions. The ideal candidate brings deep expertise in thermal, mechanical, and heat mitigation solutions for memory product. They demonstrate strong analytical and problem-solving skills. They have a proven record of delivering products from concept through high-volume manufacturing! Performs design and development engineering assignments related to hardware products and systems including development of new products or updates to existing products. Work may encompass one or more areas of engineering including electronic design, mechanical design, or other related fields. Duties may include research, evaluation, development, and application of new processes and methods into products. May be responsible for establishing and conducting testing routines, developing or implementing project plans, budgets, and schedules, and documentation

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Design Technology Co-Optimization (DTCO) team works at the intersection of process technology, standard cell architecture, and design implementation to optimize power, performance, and area (PPA) for advanced memory products. The team collaborates closely with standard cell library, RTL, and physical design engineers to evaluate design tradeoffs and develop methodologies that improve silicon outcomes. As a DTCO Intern, you will gain hands-on experience assessing and optimizing PPA at the standard cell and logic block level. You will use industry-standard place-and-route tools and AI-enabled automation techniques to implement, benchmark, and optimize logic blocks while developing practical skills in physical design, timing closure, and design analysis. Responsibilities Implement standard cell logic blocks using industry-standard physical design tools, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization activities focused on PPA assessment. Analyze and benchmark power, performance, and area across standard cell libraries and logic block configurations, identifying opportunities for improvement. Perform static timing analysis (STA), investigate setup and hold timing violations, and support timing closure activities. Execute physical verification checks, including DRC, LVS, and IR-drop analysis, and assist with resolving design issues. Leverage Generative AI, AI Assistants, and Agentic AI solutions to automate data collection, reporting, comparison, and w

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an Physical Design Engineer to lead cross-functional efforts to solve complex physical design challenges and develop end-to-end RTL-to-GDS methodologies across advanced nodes, with a strong focus on PPA and runtime improvements. The engineer will architect, integrate, and deploy AI/ML-driven solutions into production physical design flows, creating custom CAD tools and partnering with internal teams and EDA vendors to drive next-generation, ML-enabled capabilities. This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are BS in Electrical or Computer Engineering (or equivalent experience) with 5+ years in Physical Design CAD methodology at advanced nodes. Proven track record improving PPA and/or runtime on high-performance, low-power taped-out designs. Hands-on with industry-standard EDA tools (e.g., Fusion Compiler) across synthesis, P&R, STA, signoff, and hierarchical flows. Strong Python/Tcl and data skills, with interest or experience in ML frameworks (PyTorch, TensorFlow), and the ability to drive complex projects independent

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking talented Physical Design Engineers to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team. This role is hybrid , based out of Austin, TX, Santa Clara, CA or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts. Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration. Strong problem solver who excels at debugging complex issues across design hierarchies. Collaborative team player who thrives in fast-paced, technically challenging environments. What We Need BS/MS/PhD in EE/ECE/CE/CS with proven experience in synthesis, PnR, and timing closure on taped-out designs. Expertise with industry-

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we build open, state of the art compute for real workloads and real developers. You will own CPU core-level testbench development and verification, shaping how our out-of-order RISC-V CPUs behave in silicon. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring 8+ years in CPU verification, CPU testbench development, or closely related digital design. You have deep hands-on experience building and owning CPU core-level testbenches, not just using existing environments. You know high-performance out-of-order CPU microarchitecture in depth. You are comfortable developing testbench infrastructure in CVM methodology, with UVM experience as a strong plus. You work comfortably across RTL, waveforms, logs, regressions, and cross-functional debug with design, DV, emulation, and post-silicon teams. You are comfortable using AI-assisted verification workflows to improve debug, stimulus creation, and coverage analysis, while applying strong engineering judgment to validate results. What We Need Lead hands-on CPU core-level testbench development for hi

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we build open, state of the art compute for real workloads and real developers. You will own CPU focused test generator development and verification strategy, shaping how our out-of-order RISC-V CPUs are validated against complex ISA and microarchitectural behavior. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring 8+ years in CPU design verification, test generation, or closely related CPU validation work. You have led development of test generators for x86, ARM, or RISC-V ISA environments. You understand CPU ISA behavior, privileged architecture, and high-performance out-of-order CPU microarchitecture. You are comfortable building tools, stimulus, and automation that scale verification across large CPU programs. You communicate clearly across design, DV, architecture, emulation, and post-silicon teams. What We Need Lead development of CPU core-level test generators for high-performance out-of-order RISC-V cores. Own generator strategy, infrastructure, and methodology for ISA and microarchitectural verification in both pre-silico

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a Principal Analog Design Engineer to lead the design, integration, and delivery of advanced analog and mixed-signal IPs for High Bandwidth Memory (HBM) products. This role is critical in developing and integrating high-performance analog subsystems within the HBM logic die, enabling industry-leading bandwidth, power efficiency, and reliability. As a principal engineer, you will provide deep technical leadership across analog design, IP integration, system alignment, and silicon execution, driving end-to-end success of HBM solutions. Responsibilities will include, but are not limited to: Lead the d esign and own critical HBM analog circuits, including: High ‑ speed transmitters and receivers Clock generation and distribution (PLLs, DLLs, CDRs) SerDes ‑ related analog blocks Biasing, reference, and calibration circuits

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron’s High‑Bandwidth Memory (HBM) Digital Design organization is seeking a Digital Physical Design Engineer to drive backend implementation of high‑performance, low‑power digital logic used in advanced memory products. This role spans backend implementation from Netlist to GDSII, with a strong focus on timing closure, power integrity, and manufacturability in advanced process technologies. The successful candidate will work closely with RTL, DFT, CAD, and verification teams to deliver high‑quality physical designs, contribute to methodology improvements, and help push performance, power, and area (PPA) targets in complex, multi‑hierarchy designs. Key Responsibilities: Own and execute physical design implementation from synthesized netlist through GDSII, including floorplanning, placement, clock tree synthesis, routing, and physical signoff Utilize AI-Enabled tools in the Netlist to GDS flow Perform and drive timing closure across multiple modes, corners, and scenarios using industry‑standard STA tools Analyze and resolve congestion, timing, IR drop, EM, and power integrity issues Develop and refine floorplans, power grids, and clocking strategies for high‑performance designs Work with placement and timing closure of custom analog hard IP macros in a digital-on-top design flow Collaborate closely with RTL designers to influence partitioning, constraints, and micro‑architecture decisions early in the design cycle Implement and va

At Freddie Mac, our mission of Making Home Possible is what motivates us, and it’s at the core of everything we do. Since our charter in 1970, we have made home possible for more than 90 million families across the country. Join an organization where your work contributes to a greater purpose. We are accepting applications for this position until 10/16/2026 Position Overview: Looking for a company to help prepare you for a successful career? Our Multifamily Division at Freddie Mac is searching for dedicated, creative, and adaptable individuals to support the division's Marketing and Communications team in the education and training space. In this role, you will design and develop training content, support educational events, and collaborate with business stakeholders to deliver engaging learning experiences for both internal and external audiences. You'll gain hands-on experience in instructional design, event planning, project management, and client engagement while contributing to Freddie Mac's mission-driven work. Our Impact: Freddie Mac Multifamily's Marketing and Communications team helps drive business and highlights the value of the Multifamily mission for our customers and partners. You'll be part of a team that engages lenders and promotes our rental housing financing business and its impact on renters and communities nationwide. As one of the nation's largest sources of funding for Multifamily housing—particularly affordable housing—we are committed to making a meaningful difference through education, communication, and innovation. Your Impact: Design and develop engaging learning content and training materials that align with business and client objectives. Create educational content using tools such as PowerPoint, Canva, Adobe Creative Suite, and other digital learning

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About Ramp Ramp is building the smart infrastructure for finance teams, embedded in the transaction flow of every dollar a business spends. We automate how over $200B in annualized spend flows in and out of 70,000+ companies: authorizing payments, flagging risk, categorizing spend, and closing books. The problems are high-stakes, data-dense, and unforgiving. We hire people with high agency and high urgency. We look for slope over intercept. We care less about where you trained and more about what you’ve built. At Ramp, everyone is a builder who owns problems end to end and makes consequential decisions that shape the outcome. The median Ramp customer saves 5% and grows revenue 16% in their first year – far in excess of businesses operating without Ramp. We believe every ambitious company deserves the same. If you want to build systems that directly shape how companies move and manage billions, Ramp is the place to do it. About the Role Design is core to how we build products at Ramp. We're hiring a recruiter to help shape the team that will be responsible for it. You'll partner with design leadership to hire across Product Design, Design Engineering, and Brand Design. You'll lead searches from inception to close, helping teams identify, assess, and hire exceptional designers. The best designers are rarely on the market. A big part of the job is fostering relationships before someone starts their job search: through events, referrals, and ongoing engagement with the design community. You'll help Ramp stay connected to talent and cultivate the networks that drive future hiring. What You’ll Do Own full-cycle recruiting across Product Design, Design Engineering, and Brand Design Partner with design leadership to define hiring needs, align on candidate profiles, and calibrate talent across a range of design disciplines Identify and engage talent through X, portfolio sites, and other industry channels Build relationships with designers through referrals, events, and ongoi