Design Verification Lead in United States

About the Team: OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale. In this role you will: Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality. Define verification plans based on architecture and microarchitecture specs. Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies. Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness. Drive bug triage, root cause analysis, and work closely with design teams on resolution. Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments. You might thrive in this role if you have: BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification. Proven success verifying complex IP or SoC designs in industry-standard flows Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi). Strong knowledge

Job Details: Job Description: Do Something Wonderful At Intel, we put silicon at the center of the world’s most meaningful innovations. From personal computing and AI to cloud-scale data centers and edge platforms, our processors power technologies that touch billions of lives. If you’re passionate about building world-class silicon at massive scale, we want to build the future with you. The Team You’ll join Intel’s All Cores Engineering (ACE) organization, the team responsible for designing and delivering Intel’s industry‑leading CPU cores. Within ACE, the Atom group focuses on high‑efficiency, performance‑per‑watt optimized cores that enable everything from client platforms to emerging edge and scalable solutions. This is a hands‑on senior engineering role with direct impact on next‑generation CPU silicon. What You’ll Do As a Senior CPU Design Verification Engineer you will play a critical role in ensuring architectural correctness, functional robustness, and power‑efficient performance of Intel’s Atom CPU designs before first silicon. Key responsibilities include but not limited to the following: Lead pre‑silicon functional verification of complex CPU and SoC logic to ensure full compliance with architectural and microarchitectural specifications. Develop and execute verification plans, testbenches, and SystemVerilog/UVM environments, ensuring comprehensive functional and coverage closure. Define, run, and analyze system‑level simulations to uncover functional, performance, power, and corner‑case issues. Debug and root‑cause complex RTL, microarchitecture, and integration issues; drive issues to resolution with design teams. Collaborate cross‑functionally with CPU architects, RTL de

About the Team OpenAI develops models that can reason through complex problems and hardware designed for the demands of advanced AI. AI for Chips connects these efforts: applying increasingly capable AI systems to the work of semiconductor engineering. Our goal is to help engineers develop better chips and shorten design cycles. This work brings research, model training, and hardware expertise together to build tools that engineers can use on real designs, with correctness and measurable performance at the center. About the Role We’re hiring a Research Engineer to help OpenAI models solve chip-design problems through reinforcement learning, tool use, and evaluation. You’ll own experiments from the initial idea through implementation and analysis. That means building environments and evaluations, running training, investigating failures, and using the results to decide what to try next. You’ll also build the software needed to make those experiments reliable and reproducible. We value strong coding fundamentals, careful experimental judgment, and the ability to make progress independently. Prior chip-design experience is helpful, but you can learn the domain alongside the team’s hardware specialists. In this role, you will: Build RL environments and evaluations for tasks such as RTL generation, design verification, and physical design optimization. Develop and test approaches that help models use chip-design tools and improve power, performance, and area while preserving correctness. Design experiments, establish baselines, and measure whether improvements hold up on new tasks and designs. Investigate failures across model behavior, rewards, evaluation tools, and experiment infrastructure. Improve iteration speed through better tooling, faster evaluations, and proxy rewards that reflect the outcomes we care about. Turn successful experiments into reusable research code and training workflows, working closely with researchers and engineers. You might thrive in this ro

What you’ll do Execute weekly system-level exploratory testing across the scanner and supporting software; log and triage issues with clear reproduction steps. Work with engineering to debug root cause and validate fixes. Help maintain the DHF and traceability between user needs, design requirements, tests, and results. Own practical test execution logistics (fixtures, test data, environments, calibration artifacts) and keep things repeatable. Help build the continuous testing strategy: automated tests where feasible, plus structured manual and system tests. Support V&V activities, including coordination with external partners as needed. What we’re looking for Strong hands-on testing instincts for complex electromechanical systems with substantial software. Ability to write clear bug reports and communicate risk/impact. Experience building and maintaining test plans/protocols; comfort operating lab equipment and debugging across layers. Useful experience Experience testing complex systems end-to-end (automation where it pays off, plus hands-on hardware/instrumentation). Medical device or other safety-critical environments and comfort translating risk into practical test coverage.

Experienced or Senior Digital Design Engineer Company: The Boeing Company Boeing Defense, Space & Security (BDS) seeks a Digital Design Engineer to join our team in Huntsville, AL and play a vital role in the Patriot Advanced Capability-3 (PAC-3) program, one of the world's most advanced air and missile defense systems. This is your opportunity to work in a dynamic environment where your skills will directly contribute to protecting critical assets and ensuring mission success. If you are passionate about defense technology and want to make a real impact, we want to hear from you! Position Responsibilities: Design high speed digital circuits and perform signal integrity analysis Focus on electronic systems and electrical design, simulation and verification/validation testing of high-speed printed circuit boards (PCB) throughout full product development cycle Providing design guidelines and support for system architecture design, board layout, product bring-up, debug, validation, and factory builds This position requires obtaining a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim U.S. secret clearance Pre Start and final U.S. secret clearance Post Start is required. Basic Qualifications (Required Skills/Experience): Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement 3 or more years of related work experience Experience in digital circuit design Preferred Qualificatio

Job Details: Job Description: About the Role Join a team developing next-generation CPU cores that power client, server, IoT, and AI platforms. As a Senior Physical Design Engineer (CPU), you will play a key role in delivering high-performance, power-efficient silicon solutions. You will take ownership of blocks within the CPU core design, driving implementation from RTL to GDS and contributing to advanced physical design methodologies. What You’ll Do Key responsibilities will include but not limited to: Own physical design and implementation of CPU core blocks or subsystems Execute synthesis, floorplanning, place and route, and design closure Perform static timing analysis (STA), power analysis, and physical verification Drive convergence of timing, power, and area (PPA) metrics Debug and resolve complex design issues across multiple design stages Develop and optimize design flows and automation scripts Collaborate cross-functionally with RTL design, verification, clocking, and full-chip teams Contribute to improving design methodologies and best practices Provide guidance to junior engineers where applicable Behavioral traits that we are looking for: Strong problem-solving and analytical thinking Takes ownership and accountability for deliverables Collaborates effectively across multidisciplinary teams Communicates technical concepts clearly and concisely Prioritizes work effectively in a fast-paced environment Continuously learns and applies new tools and methodologies Why Join Us Work on cutting-edge CPU core designs that power client, server, IoT, and AI platforms used worldwide Be part of

Experienced or Senior Digital CCA Design Company: The Boeing Company Boeing Defense, Space & Security (BDS) seeks a Digital CCA Design Engineer who is a subject matter expert in high-speed digital circuit design , signal integrity analysis , and electrical design to join our time in Huntsville, AL. This position will p lay a vital role in the Patriot Advanced Capability-3 (PAC-3) program, one of the world's most advanced air and missile defense systems. This is your opportunity to work in a dynamic environment where your skills will directly contribute to protecting critical assets and ensuring mission success. If you are passionate about defense technology and want to make a real impact, we want to hear from you! Position Responsibilities: Focus on electrical design, simulation, verification, and validation testing of high-speed printed circuit board design and electronic system Lead product development cycles Collaborate with cross-functional teams, including other engineering disciplines Keeping current on related industry best practices and technological advancements This position requires obtaining a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim U.S. secret clearance Pre Start and final U.S. secret clearance Post Start is required. Basic Qualifications (Required Skills/Experience): Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement. 3 or more years of related experien

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for a software engineer to help build the design methodology, software abstractions, and infrastructure that enable a small silicon team to develop complex chips rapidly and with high confidence. You will turn evolving architecture and design needs into reusable tools and workflows that improve iteration speed, quality, and then apply those tools to help construct world-class silicon. You’ll work closely across architecture, design, verification, performance modeling, and systems software. This role is well suited for an engineer who enjoys building high quality software and is motivated by the challenge of improving velocity and quality of the silicon development process. In this role, you will: Develop and scale design methodologies for rapid first-party chip development and apply them to construct complex custom chips Create abstractions that allow hardware structures, configurations, experiments, and results to be represented consistently across tools. Automate high-value engineering workflows and improve their reproducibility, observability, testability, and ease of use. Partner with architects, RTL designers, verification engineers, compiler engineers, and systems software engineers to gather requirements and then implement solutions. Use methodology and tooling to identify design risks early, accelerate iteration, and improve confidence in performance and implementation tradeoffs. Contribute across multiple aspects of software and hardware

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale. This is a senior, hands-on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure, physical design convergence, bring-up, and production readiness. You will plan and oversee the work of junior engineers and help drive and develop productive engineering relationships with external partners and help manage partner execution. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic as well as off-chip protocol bridges and interfaces. Drive third party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and de

About the Team OpenAI develops models that can reason through complex problems and hardware designed for the demands of advanced AI. AI for Chips connects these efforts: applying increasingly capable AI systems to the work of semiconductor engineering. Our goal is to help engineers develop better chips and shorten design cycles. This work brings research, model training, and hardware expertise together to build tools that engineers can use on real designs, with correctness and measurable performance at the center. About the Role We’re hiring a Software Engineer to build the research infrastructure and tooling that help OpenAI models design silicon. You’ll turn chip-design workflows into reliable environments for reinforcement learning and evaluation, and make it easier for researchers to run experiments and iterate on new ideas. You’ll move between software engineering, tool integration, and open research problems. We value strong coding fundamentals, clear technical judgment, and independent execution. Prior chip-design experience is helpful, but you can learn the domain alongside the team’s hardware specialists. In this role, you will: Build and maintain infrastructure for reinforcement learning environments, evaluations, and long-running experiments. Integrate electronic design automation (EDA) tools into workflows for RTL generation, verification, and physical design optimization. Improve experiment reliability, reproducibility, observability, and performance; debug failures across tools, services, and infrastructure. Develop tooling and model harnesses that let researchers test ideas quickly and measure correctness and power, performance, and area (PPA). Collaborate with researchers and engineers to turn successful experiments into reusable systems and training workflows. Own ambiguous projects end to end, communicate progress, and use results to guide the next iteration. You might thrive in this role if you: Have strong software engineering fundamentals, with

NVIDIA is seeking an a PCB Library Engineer to join our PCB Design Infrastructure team. In this role, you will help develop and maintain the PCB library assets used across NVIDIA's Data Center, AI, Networking, Automotive, and Graphics products. Working alongside experienced PCB designers, library engineers, mechanical engineers, manufacturing engineers, and component engineers, you will create and validate component footprints, schematic symbols, mechanical components, panel definitions, and other critical design assets that enable successful product development. This position provides an excellent opportunity to build expertise in PCB design, manufacturing, component engineering, and design automation while supporting some of the most advanced computing platforms in the world. What you'll be doing: Develop PCB footprints, padstacks, schematic symbols, and mechanical library content using Cadence PCB design tools. Review component datasheets, package drawings, and engineering specifications to create accurate design libraries. Support library verification, release, and documentation processes. Partner with PCB design, mechanical engineering, manufacturing engineering, and operations teams to resolve library-related issues. Learn and apply industry standards, including IPC requirements, DFM, DFA, and DFT principles. Support quality initiatives to ensure library content is accurate, manufacturable, and scalable. Participate in continuous improvement and automation efforts within the library environment. Develop a strong understanding of PCB fabrication, assembly, and component technologies. What We Need to See: BS degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, Manufacturing Engineering, or a related field or equivalent experience. <p

1743 - This position is in Austin, Texas. Position Summary We are seeking an experienced Board-Level Hardware Validation Engineer to define and execute the validation and verification of complex electronic systems throughout the product lifecycle. This role is responsible for defining validation strategies, developing test plans, executing hands-on testing, analyzing failures, and working directly with ODM partners to ensure products meet performance, reliability, quality, and compliance requirements before mass production. The ideal candidate combines strong electrical engineering fundamentals with practical lab expertise and is comfortable personally performing validation activities while coordinating with cross-functional teams and manufacturing partners. Key Responsibilities Validation Strategy & Planning Define comprehensive board-level and inter-board validation plans based on product requirements, design specifications, and customer use cases. Develop validation methodologies covering functional, electrical, thermal, power, signal integrity, reliability, and stress testing. Establish test coverage, acceptance criteria, qualification requirements, and release gates. Review hardware architecture, schematics, component specifications, and interface topologies to identify validation risks early in the design cycle. Define incremental validation and regression coverage for component substitutions, design changes, and firmware updates. Hands-On Validation Execution Develop, automate, and execute validation tests on prototype and production-intent hardware. Perform board bring-up, functional verification, electrical characterization, and system-level integration testing. Validate communication interfaces, control signals, and timing requirements. Verify power sequencing, reset behavior, leakage current, and recovery across operating states. Execute temperature and voltage corner testing against approved operating limits. Use oscilloscopes, logic an

Experienced Electrical & Test Engineer Company: The Boeing Company Boeing Defense, Space & Security (BDS) seeks an Experienced Electrical and Test Engineer to serve as an Automated Test Equipment Engineer to join our Patriot Advanced Capability-3 (PAC-3) Electrical Engineering Capability Team in Huntsville, AL . We design, sustain, and upgrade next generation electronics concepts and support production and special test equipment design for increasing capacity requirements. Position Responsibilities: Support design of automated test equipment, development of engineering documentation, and hardware fabrication, integration, and validation testing Develop, document, and maintain electronic and electrical system requirements according to customer desires and contract requirements Create and implement overall Test Equipment Design strategies Review and apply real-time test anomaly troubleshooting and resolution of issues encountered during hardware validation and verification testing Support fielded test equipment hardware and software over the entire product lifecycle Research emerging technologies for potential applications to meet projected requirements Perform Root Cause Corrective Action (RCCA) investigations, troubleshooting, and resolutions This position requires the ability to get a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim U.S. secret clearance Pre Start and final U.S. secret clearance Post Start is required. Basic Qualifications (Required Skills/Experience): Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Sc

What you’ll do Partner with medical image reconstruction scientists / engineers to build ML components that improve reconstruction quality, speed, robustness, or quantitative accuracy. Define training/evaluation pipelines, datasets, and metrics that map to user needs and design requirements. Productionize models: inference performance, reproducibility, monitoring for drift/regressions, and safe fallbacks. Collaborate on hybrid algorithms, incorporating physics and learned priors, denoisers, learned regularizers, and quality estimation. Help build tooling for rapid experimentation as well as rigorous verification of algorithm changes. What we’re looking for Strong applied ML experience plus comfort with signal processing / imaging or adjacent domains. Ability to move fluidly between research prototypes and production-quality systems. Strong evaluation discipline: metrics, ablations, data leakage avoidance, and reproducibility. A demonstrated track record of applying ML to physics-based or inverse problems (i.e., shipped projects, a portfolio, or publications.) Useful experience ML for imaging/inverse problems (or adjacent) with strong evaluation discipline and comfort with GPU performance constraints. Pragmatic production mindset: reproducible training/inference, regression testing, and safe deployment in high-stakes contexts. A background in computational physics or scientific computing. Leverage ML-based methods such as PiNNs and Neural Operators to solve partial differential equations arising in ultrasound simulation and imaging. Experience in Agentic-SciML is a plus. Hands-on experience with data curation for ML: building datasets from messy, real-world sources, defining ground truth, and managing labeling or simulation pipelines. Background in data assimilation: combining observations with physics-based models (Kalman filtering, variational methods, ensemble approaches, or learned variants).

Mid-Level or Senior Aerospace Systems Safety Engineer Company: The Boeing Company The Boeing Defense Air Dominance Division Systems Safety & Mission Assurance organization is looking for an Aerospace Systems Safety Engineer to join our team in Hazelwood, MO . Our teams are currently hiring for a broad range of experience levels including Experienced (Level 3) or Senior (Level 4) Aircraft Safety Engineers. A successful candidate will perform system software safety engineering work on a Proprietary Air Dominance program, drive hazard analyses, demonstrate compliance to MIL‑STD‑882E and other standards, and influence system architecture to reduce safety risk. The selected candidate will provide technical guidance and perform critical Software System Safety Engineering work. In addition to working with System Safety personnel, the individual will work extensively with design, development, and test to incorporate robust safety features and reduce project safety risk. Primary responsibilities: Analyzes the integration of complex airplane systems and their corresponding airplane-level effects, failure indications, and flight crew actions as part of a system of systems analysis Documents safety analyses, hazard mitigation, validation, and verification activities in compliance with relevant customer and regulatory safety standards such as MIL-STD-882E, MIL-HDBK-516C, AC-17-01, DO-178C, and DO-254. Demonstrates safety hazard risk mitigation and control methods to the customer and regulators Identifies safety issue systemic root causes and recommends corrective actions using industry best practices Collaborates with internal and external stakeholders to define, validate, and inte