Engineer 2 in United States

We're building the platform that lets long-running autonomous agents operate safely inside NVIDIA's enterprise. These are not assistants on a developer's laptop. They are fleets of agents deployed in the cloud, running continuously at scale on shared accelerated compute. They take on real work across enterprise systems, so people get far more done than they could before. This role defines the constructs that agents are built from: the blueprints they start from, the tools, skills, and plugins that power them against enterprise data, the runtime safety harness that keeps them in bounds, and the connections into credential management, sandbox, memory, and observability. The team designs and ships these building blocks so that agent developers across the company can stand up a new agent, wire it in, and run it for days or weeks. Security and safe execution come out of the box, not something each team has to get right on its own. Today an agent runs inside a single harness. Claude, Codex, and open-source agent harnesses each work differently underneath, with their own execution model, tool interface, and telemetry shape. The platform smooths over those differences, so a single skill, safety policy, or trace works the same no matter which harness is running. We want to enable agents that act on a person's behalf, governed and secure, continuously evaluated and self-improving. These agents coordinate and hand work off to each other, with identity and policy following every hop. They route and tune themselves across harnesses from live eval signals, and get better from their own production telemetry instead of waiting on a human to retrain them. Have you run agents on a harness like Claude or Codex and hit the walls that show up when they run for real, for days, against live systems — and wanted them to learn from it on their own? We're building the platform that solves those problems once, for every team. What you'll b

The DFP Engineer – Manufacturing role defines and implements the validation and screening of new silicon features within high‑volume manufacturing flows. You will translate product requirements into executable test methodologies, infrastructure, and detailed manufacturing test plans that ensure quality, yield, and efficiency at scale. This role sits at the intersection of multiple multi-functional teams to make manufacturing test an outstanding part of the overall codesign and DFP lifecycle. What you will be doing: Own end-to-end manufacturing test methodology across all test stages. Translate system specs and product POR into DFP requirements, test content, coverage, and flows. Define and maintain the DFP roadmap, including infrastructure and turning point planning. Partner multi-functionally to implement test content, debug hooks, and coverage improvements. Drive alignment on manufacturability, test time, binning strategies, and cost vs. coverage trade-offs. Embed testability requirements into design to enable robust screening and debug. Define data and analytics frameworks to support yield analysis and continuous improvement. Lead DFP documentation as the single source of truth and feed findings into future methodologies. What we need to see: MS in Electrical Engineering, Computer Engineering, or related field (or equivalent experience) 6&#43; years in silicon post‑silicon validation and/or high‑volume manufacturing test for complex SoCs, GPUs, CPUs, or similar. Hands‑on experience with test content bring‑up, limit setting, correlation to characterization, and yield/coverage optimization. Proficiency with scripting and data analysis (e.g., Python, MATLAB, R, SQL) for test data analytics, limit tuning, and yield/debug analysis. <

Build the infrastructure that keeps every NVIDIA chip aligned from first spec to final shipment. NVIDIA's Silicon Co-Design Group sits at the convergence of architecture, silicon, systems, and manufacturing. The System–Manufacturing Architecture (SMAC) team coordinates between system specifications and manufacturing test specifications from pre-silicon POR through production release across GPU, SoC, and CPU programs. When that alignment drifts, silicon faces the consequences: escapes, yield loss, and performance loss. We're hiring a Senior Manufacturing & System Co-Design Workflow Engineer to lead the methodology and infrastructure that maintains holistic, systematic alignment, at scale across the full portfolio. The strongest candidates in this role design the workflow before being asked to fix a program, and build the checks and automation that confirm alignment holds long after they've moved on to the next problem. What you’ll be doing: SMAC Workflow Methodology: Define manufacturing spec types, including schema and semantics, derived from system PORs and features. Own the methodology that governs how specification work gets structured, versioned, and validated across the program lifecycle. Production Python Pipelines & Automated Checks: Develop production-grade Python pipelines and automated checks that catch specification drift between system POR and manufacturing test programs ,ATE, SLT, BLT, L10&#43;, before silicon exposes the discrepancy. The goal is that misalignments surface in the workflow, not on the tester. E2E Program Integration & TPM Attestation: Wire SMAC work into the end-to-end program spine, milestones, gates, and artifacts, and define explicit TPM-driven attestation when checks lag. Alignment can't be assumed; it must be proven at every stage. Agent-Ready Tooling & CI Infrastructure: Integrate tooling into an agent-ready

At NVIDIA, we push the boundaries of computing innovation. Our ASIC Verification Engineers focus on developing the world’s top SoCs and GPUs. Joining us as a Senior ASIC Verification Engineer - GPU means working on modern technology powering consumer graphics and AI applications. This position is ideal for those passionate about technology and eager to impact computing’s future. What you'll be doing: As a key member of our ASIC Verification team, you will verify the design and implementation of the industry's leading GPUs. You will be responsible for verifying the ASIC build, architecture, golden models, and micro-architecture using advanced verification methodologies such as UVM or equivalent. Understand the design and implementation of your unit/cluster/chip, define the verification scope, develop the verification infrastructure, and verify the correctness of the design. Collaborate with architects, designers, and pre- and post-silicon verification teams to accomplish your task. What we need to see: Bachelor's Degree in EE, CS, or CE or equivalent experience. 5&#43; years of relevant experience. Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies. Experience with design and verification tools (VCS or equivalent simulation tools, debug tools like Verdi, Indago, GDB). Expertise in System Verilog or similar HVL. Strong debugging and analytical skills. Perl and C/C&#43;&#43; programming language experience desirable. Strong communication skills and the ability & desire to work as a great teammate are huge pluses. Experience in crafting test bench environments for unit and system level verification. #LI-Hybrid Your base salary will be det

NVIDIA silicon runs the world's AI infrastructure. The frequency it delivers across every voltage, process corner, and workload is not assumed. It is measured, correlated, and validated. This role does that work. The Silicon Co-Design Group is where architecture intent becomes silicon reality. We own the boundary between what was designed and what was built, and we are the team that knows the difference. When a program ships at frequency and at quality, this team is a reason why. You will be the person who follows through between simulation and silicon. When the model is wrong, a frequency corner that doesn't hold, a Vmin that walks, a critical path that timing analysis missed, you find out why, and your data is what the rest of the program acts on. Architecture, design, and product teams do not guess. They use your numbers. The engineers who do this well are rare. They think like circuit designers, work like experimentalists, and reason like data scientists. If that is you, read on. What you'll be doing: Own silicon speed characterization from first power-on through production sign-off, covering frequency, Vmin, Vmax, and timing margins across the full PVT space. Close the correlation gap. Tie pre-silicon timing analysis and critical path predictions to measured silicon, quantify where the model diverges from reality, and produce analysis that architecture and design can act on with confidence. Trace failures to their source, whether a microarchitectural bottleneck, a critical path that doesn't close under voltage, a clocking issue, or a process corner the model didn't anticipate, and drive the resolution. Own and build AI agents that work at your direction: automated test orchestration, intelligent data pipelines, and analysis flows that expand coverage and compress cycle time without sacrificing difficulty. Know where AI accelerates real work and whe

NVIDIA is seeking elite ASIC Verification Engineers to verify the design and implementation of the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will help to build the high-performance processor elements that implement programmable compute and graphics functionality. What you'll be doing: As a key member of our ASIC Verification team, you will verify the design and implementation of the industry's leading GPUs You will be responsible for verification of the ASIC design, architecture, golden models and micro-architecture using advanced verification methodologies such as UVM Understand the design and implementation of your unit, define the verification scope, develop the verification infrastructure and verify the correctness of the design Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks What we need to see: Bachelors Degree in EE, CS or CE or equivalent experience 2&#43; years of relevant experience Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies Background with design and verification tools (VCS or equivalent simulation tools, debug tools like Verdi, GDB) Experience crafting test bench environments for unit and system level verification Strong background in System Verilog or similar HVL Expertise with C/C&#43;&#43; programmin

What if the work you did every day could impact the lives of people you know? Or all of humanity? At Illumina, we are expanding access to genomic technology to realize health equity for billions of people around the world. Our efforts enable life-changing discoveries that are transforming human health through the early detection and diagnosis of diseases and new treatment options for patients. Working at Illumina means being part of something bigger than yourself. Every person, in every role, has the opportunity to make a difference. Surrounded by extraordinary people, inspiring leaders, and world changing projects, you will do more and become more than you ever thought possible. We are seeking a Senior Mechanical Engineer to support new product development in genomics instrumentation. This is a highly technical mechanical design role focused on the development of custom mechanisms, precision motion systems, and electromechanical assemblies used in advanced instrumentation. The ideal candidate will be an engineer with experience designing motorized mechanisms and precision motion systems, including a strong understanding of system requirements, motion architecture, controls integration, structural design, and performance validation. The ideal candidate also has experience developing motion solutions from requirements through implementation and understands the engineering principles behind achieving precise, reliable motion in complex systems. Responsibilities Design and develop custom mechanical mechanisms for use in genomics instruments, including motion systems, precision assemblies, and fluidic or sample‑handling components. Integrate mechanical designs with electrical, firmware, and control systems Create and maintain 3D CAD models, engineering drawings, and support

What if the work you did every day could impact the lives of people you know? Or all of humanity? At Illumina, we are expanding access to genomic technology to realize health equity for billions of people around the world. Our efforts enable life-changing discoveries that are transforming human health through the early detection and diagnosis of diseases and new treatment options for patients. Working at Illumina means being part of something bigger than yourself. Every person, in every role, has the opportunity to make a difference. Surrounded by extraordinary people, inspiring leaders, and world changing projects, you will do more and become more than you ever thought possible. Summary The Staff Data Engineer is a seasoned, hands-on engineer who designs, builds, and scales data products on our cloud lakehouse, powering analytics, reporting, and AI/ML across Illumina. We are looking for someone with strong proficiency in Python, SQL, and data modeling, a solid understanding of distributed systems and system design who has built and scaled data products on modern cloud platforms such as Databricks and Snowflake. This is a hands-on, senior individual-contributor role with end-to-end ownership and leadership spanning multiple domains such as Supply Chain, Manufacturing and Quality, including mentoring engineers on our global (India-based) team. Responsibilities Partner across business, AI, and platform teams translating domain needs (e.g., SAP, Manufacturing, Quality) into well-modeled, governed and scalable data products. Design, build, and scale end-to-end data products on Databricks (and interoperating with Snowflake) — from ingestion through curated, analytics-ready datasets following a medallion (Bronze/Silver/Gold) architecture. Develop reusable frameworks, libraries, and

About Pinterest: Millions of people around the world come to our platform to find creative ideas, dream about new possibilities and plan for memories that will last a lifetime. At Pinterest, we’re on a mission to bring everyone the inspiration to create a life they love, and that starts with the people behind the product. Discover a career where you ignite innovation for millions, transform passion into growth opportunities, celebrate each other’s unique experiences and embrace the flexibility to do your best work. Creating a career you love? It’s Possible. At Pinterest, AI isn't just a feature, it's a powerful partner that augments our creativity and amplifies our impact, and we’re looking for candidates who are excited to be a part of that. To get a complete picture of your experience and abilities, we’ll explore your foundational skills and how you collaborate with AI. Through our interview process, what matters most is that you can always explain your approach, showing us not just what you know, but how you think. You can read more about our AI interview philosophy and how we use AI in our recruiting process here . The Programmatic Ads team integrates with external demand partners (DSPs, SSPs, etc) through OpenRTB. We drive performance optimization (latency, conversion, engagement, fill rate, etc) for our programmatic ad products. We are also responsible for building internal tools to better enable cross-functional teams. What you’ll do: Lead one or two partner integrations, and work closely with product managers, data scientists, other cross-functional teams, and external partners to understand business requirements and translate them into technical solutions. Use AI to accelerate team execution, system design, and decision-making, applying sound judgment to validate outputs and ensure correctness and quality. Independently drive the full software development lifecycle, including ideation, technical design, prototyping, development, and release. Ind

A World-Changing Company Palantir builds the world’s leading software for data-driven decisions and operations. By bringing the right data to the people who need it, our platforms empower our partners to develop lifesaving drugs, forecast supply chain disruptions, locate missing children, and more. The Role As a Security Systems Engineer at Palantir, you are responsible for implementing, designing, and maintaining the physical security systems that ensure the protection of Palantir’s people, assets, intellectual property, and reputation. You lead research and evaluations for the latest technology, security infrastructure, policies, procedures, systems, and applications, looking for easy-to-use capabilities that reduce button clicks and ultimately give time back to the operator. You will be collaborating with technical teams to develop and maintain end-to-end project plans and ensure on-time delivery. Your technical expertise is second only to your integrity and genuine passion for security and technology. As a member of the Global Security and Investigations team, you work with security professionals, architects, lawyers, and software and network engineers to deliver a safe and secure environment for your fellow employees. Palantir is a global company, so you'll lead physical security projects all over the world. You'll work hard to break down barriers between teams by communicating your knowledge and goals effectively across time zones and other physical and virtual barriers. *Please note this role is NOT for cyber security or information security positions* Core Responsibilities Design and oversee the technical aspects of your projects from conception to full deployment. Systems naturally break and need maintenance. You'll work with vendors and end users to find the best solutions for a problem, in the shortest possible time. Leverage both system and software engineering skills in order to address the needs of all teams within Globa

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a mid- to senior-level Physical Design Engineer who will contribute to the physical design of high-performance chips for industry-leading AI/ML architectures, spanning implementation from synthesis through tapeout. You will partner with front-end and physical design engineers to optimize floorplanning, timing, power, performance, and area across multiple IPs. Along the way, you will build end-to-end ASIC expertise while learning from experienced engineers across the chip development process. This role is hybrid , based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An engineer excited to work on high-performance designs for industry-leading AI/ML architectures. A collaborative problem solver who enjoys working with experienced engineers across ASIC disciplines. Grounded in logic design fundamentals and gate- and transistor-level implementation. Curious about how early architectural and RTL decisions shape physical implementation and final chip quality. What We Need A BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a relat

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, we are transforming how the world uses information to enrich life. The High Bandwidth Memory (HBM) Design team develops industry-leading memory solutions that enable advances in Artificial Intelligence, high-performance computing, graphics, and data-center applications. Our engineers collaborate across global teams to deliver innovative memory architectures and semiconductor technologies that power next-generation computing systems. As an HBM Design Engineer Intern, you will work alongside experienced memory engineers and gain hands-on experience in semiconductor design, simulation, verification, and analysis. This internship provides exposure to industry-standard design methodologies, EDA tools, and cross-functional collaboration throughout the product development lifecycle. You will also have opportunities to apply AI-Assisted and AI-Enabled workflows to improve engineering productivity, debug efficiency, and design quality. Responsibilities Assist with the design, simulation, analysis, and verification of HBM memory and logic circuits using industry-standard semiconductor design tools. Support RTL development, circuit implementation, timing analysis, power analysis, and functional validation activities. Develop scripts, automation solutions, and AI-Assisted workflows to improve design productivity, debug efficiency, and design-flow quality. Collaborate with Design, Verification, Physical Design, CAD, and Product Engineering teams on technical reviews, debug activities, and project deliv

JLL empowers you to shape a brighter way . Our people at JLL are shaping the future of real estate for a better world by combining world class services, advisory and technology for our clients. We are committed to hiring the best, most talented people and empowering them to thrive, grow meaningful careers and to find a place where they belong. Whether you’ve got deep experience in commercial real estate, skilled trades or technology, or you’re looking to apply your relevant experience to a new industry, join our team as we help shape a brighter way forward. What this job involves: This position leads operations and maintenance activities for critical building systems, managing a high-performing engineering team to ensure maximum infrastructure availability and client satisfaction. The role combines hands-on technical expertise with leadership responsibilities, overseeing both preventive and corrective maintenance programs while maintaining compliance with regulatory requirements and safety standards. Your day-to-day tasks will include: Lead operations and maintenance on assigned shift, monitoring performance and directing service requests with minimal disruption to building operations Operate and monitor critical system equipment including HVAC, UPS systems, generators, chillers, and building management systems Provide technical training and support to shift engineers and maintenance technicians while fostering team development Implement and oversee preventative maintenance programs, including scheduling, task delegation, and parts ordering Process work orders for preventative and corrective maintenance, consulting with staff to identify materials and complete documentation Respond immediately to operationa

JLL empowers you to shape a brighter way . Our people at JLL are shaping the future of real estate for a better world by combining world class services, advisory and technology for our clients. We are committed to hiring the best, most talented people and empowering them to thrive, grow meaningful careers and to find a place where they belong. Whether you’ve got deep experience in commercial real estate, skilled trades or technology, or you’re looking to apply your relevant experience to a new industry, join our team as we help shape a brighter way forward. Operating Engineer – JLL What this job involves: As an Operating Engineer at JLL, you will play a critical role in ensuring the seamless operation of building systems and maintaining exceptional tenant comfort and safety. Working under the direction of the Lead Engineer, you will be responsible for completing essential maintenance tasks, responding to tenant service requests, monitoring equipment performance, and maintaining HVAC systems across critical and commercial facilities. This position is central to JLL's commitment to delivering world-class property management services and creating environments where our clients and their tenants thrive. What your day-to-day will look like: Respond promptly to tenant service requests including temperature complaints, lighting repairs, breaker resets, furniture moving, and general maintenance needs while ensuring minimal disruption and immediate cleanup of work areas Perform preventive maintenance tasks on HVAC equipment, mechanical systems, and building infrastructure, completing task sheets and reporting any equipment problems or supply shortages to the Lead Engineer Monitor and record equipment readings, settings, and operational changes in logbooks, including HVAC start-up verification, fire pump checks, temperature readings, and static pressure measure

Job Details: Job Description: About the Role Join Intel's Client Computing and Physical AI Group and help enable the next generation of mobile and desktop client platforms. We are seeking a Senior Customer Solutions Engineer to serve as a key technical leader responsible for customer platform enablement, architecture collaboration, and execution across Intel's client platform ecosystem. In this role, you will work closely with OEM customers, engineering teams, and program stakeholders to drive the successful delivery of innovative platform technologies. You will play a critical role in platform planning, issue resolution, customer engagement, and cross-functional execution from product definition through product launch and production. What You’ll Do Key responsibilities will include but not limited to: Serve as the primary technical interface between customers and Intel engineering teams, driving platform enablement and customer success. Lead cross-functional execution across platform technologies including hardware, firmware, graphics, connectivity, and I/O technologies. Drive resolution of critical platform issues, customer escalations, and technical challenges throughout the product lifecycle. Represent customer readiness, platform health, and execution status in program reviews and leadership forums. Develop technical assessments, customer enablement plans, and supporting documentation to accelerate design wins and product launches. Drive technical program execution across customer and engineering teams by aligning milestones, dependencies, risks, priorities, and deliverables. Behavioral traits that we are looking for: Strong customer focus and the ability to build trusted partners