Engineer 4 in United States

About Ema Ema is building the world’s leading Agentic AI platform to transform enterprise productivity. We enable organizations to delegate repetitive tasks to Ema, the Universal AI Employee, delivering 10x gains in workforce efficiency, across functions. Founded by former executives from Google, Coinbase, Flipkart, and Okta, our team includes engineers from premier tech companies and graduates of Stanford, MIT, UC Berkeley, CMU, and IITs. We are backed by industry leading investors including Accel, Naspers/Prosus, Section32, and angels like Sheryl Sandberg and Dustin Moskovitz. Headquartered in Silicon Valley and with offices in London, Bangalore and Vancouver, Ema is at the frontier of what Agentic AI can do in production — we ship real systems that run real business processes at scale. Who are you? We are seeking a Software Engineer to join the Ema team. You are passionate about designing and developing maintainable software applications. You are a creative problem solver who thrives in ambiguity and can make abstract problems concrete. Most importantly, you are excited to be part of a mission-oriented, fast-paced, high-growth startup that can create a lasting impact. You will: Develop and maintain enterprise software applications, including API, data, application, and service development Write clean, efficient, and maintainable code by employing a test-driven development process. Build scalable and reliable back-end systems using languages like Go and Python Develop and maintain APIs using REST and gRPC Build and maintain scalable and extensible data schemas using PostgreSQL, Clickhouse, etc. Contribute to front-end interfaces using HTML, CSS, and JavaScript frameworks such as React or Angular Ensure that applications are secure and adhere to industry best practices Continuously improve software development processes and practices Ideally, you'd have: Bachelor's degree in Computer Science or related field. At least 4 years of relevant work experience. Solid back

The Senior Software Engineer is a senior individual contributor who drives the technical direction of backend services in Go and front-end applications in Vue.js that power the Topgolf guest experience across our venues and digital products. This role owns architecture and design decisions across the stack and influences engineering standards through technical guidance and mentorship, not formal people management. Job Responsibilities Own and implement architecture and technical design decisions for backend services and APIs in Go across one or more product areas Design and build complex, scalable front-end applications and components using Vue.js Define and evolve API contracts and integration patterns (REST and/or event-driven) across services Set and drive automated testing strategy and code quality standards across the stack Provide technical guidance and mentorship to engineers through code reviews, design discussions, and pairing Diagnose and resolve complex, cross-service production issues, improving logging, monitoring, and alerting practices Champion spec-driven development, authoring and reviewing technical specs and design docs for cross-team initiatives Evaluate and drive adoption of AI-assisted development tools (e.g., Claude Code, Cursor) to improve engineering velocity and code quality Critical Skills & Experience Requirements Professional software engineering experience Building backend services in Go Building front-end applications with Vue.js Working with AI-assisted development tools (e.g., Claude Code, Cursor) in a professional setting Providing technical mentorship or driving cross-team technical initiatives BENEFITS Free Play & 1/2 price food! Health, dental, vision, 401(k) team member match, free mental well-being platform – and that

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities include but are not limited to the following: Team oriented approach to create new strategies for DRAM DFT. New DRAM Test Flow Strategy. Fail Pattern Recognition. Improved methodology for test time reduction and improved quality. Assist in solutions to high visibility DRAM product issues. Create supporting software tools to assist in Engineering Analysis. Invent and Innovate anything and everything related to DFT. Employer will accept a Bachelor’s degree in Electrical Engineering, Computer Science, Electrical and Computer Engineering or related field. Position requires: 1) CMOS circuit knowledge 2) Basic programming skills in Python, Java, C or C&#43;&#43; 3) DRAM knowledge 4) Statistics 5) Basic lab experience or equivalent applied software profiling/analytics As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays.<s

Mid-Level or Senior Aerospace Systems Safety Engineer Company: The Boeing Company The Boeing Defense Air Dominance Division Systems Safety & Mission Assurance organization is looking for an Aerospace Systems Safety Engineer to join our team in Hazelwood, MO . Our teams are currently hiring for a broad range of experience levels including Experienced (Level 3) or Senior (Level 4) Aircraft Safety Engineers. A successful candidate will perform system software safety engineering work on a Proprietary Air Dominance program, drive hazard analyses, demonstrate compliance to MIL‑STD‑882E and other standards, and influence system architecture to reduce safety risk. The selected candidate will provide technical guidance and perform critical Software System Safety Engineering work. In addition to working with System Safety personnel, the individual will work extensively with design, development, and test to incorporate robust safety features and reduce project safety risk. Primary responsibilities: Analyzes the integration of complex airplane systems and their corresponding airplane-level effects, failure indications, and flight crew actions as part of a system of systems analysis Documents safety analyses, hazard mitigation, validation, and verification activities in compliance with relevant customer and regulatory safety standards such as MIL-STD-882E, MIL-HDBK-516C, AC-17-01, DO-178C, and DO-254. Demonstrates safety hazard risk mitigation and control methods to the customer and regulators Identifies safety issue systemic root causes and recommends corrective actions using industry best practices Collaborates with internal and external stakeholders to define, validate, and inte

Become a part of our caring community The Senior Software Engineer codes software applications based on business requirements. The Senior Software Engineer work assignments involve moderately complex to complex issues where the analysis of situations or data requires an in-depth evaluation of variable factors. The Senior Software Engineer standardizes the quality assurance procedure for software. Oversees testing and debugging and develops fixes. Researches complaints and makes necessary adjustments and/or recommendations to resolve complex software related issues. Begins to influence department's strategy. Makes decisions on moderately complex to complex issues regarding technical approach for project components, and performs work without direction. Exercises considerable latitude in determining objectives and approaches to assignments. Collaborates with Business partners and Solution and Application architects in designing software solutions Use your skills to make an impact Required Qualifications Bachelor's Degree in Computer Science or related field 5 or more years of experience designing, developing, and testing of software applications and/or infrastructure Must be passionate about contributing to an organization focused on continuously improving consumer experiences 5&#43; years’ experience with Workday integration techniques including RaaS, API, Cloud Connector, and EIB 4&#43; years’ experience collaborating with HR, Talent, Payroll, Benefits, and Learning teams 3&#43; years’ experience with Workday architecture and data structures 3&#43; years’ experience working with protected information 2&#43; years’ experience implementing Workday security including SSO and MFA Preferred Qualifications Master's

We are now looking for a Senior Deep Learning Software Engineer, PyTorch. NVIDIA is hiring software engineers to design and build tools used by AI engineers across the world to design, develop, and deploy AI applications scalable across thousands of GPUs. This position will embed you in an ambitious and diverse team that influences all areas of NVIDIA's AI platform as well as directly contributes to PyTorch, a premiere deep learning framework. In this role you will work with multiple teams at NVIDIA across fields, as well as collaborate internationally with the PyTorch community to develop the best AI platform in the world. What you will be doing: Design and build PyTorch components that run efficiently on supercomputers with 1000s-100ks of GPUs. Collaborate with NVIDIA’s hardware and software teams to improve the overall GPU performance in PyTorch. Design, build and support production AI solutions used by enterprise customers and partners. Work with internal applied researchers to improve their AI tools. What we need to see: BS in Computer Science or Engineering (or equivalent experience). 3&#43; years professional experience in deep learning. Proficient with C&#43;&#43; programming. Strong understanding of systems software and interfaces. Demonstrated experience with Thread and Distributed Parallel Programming Demonstrated background developing large software projects. Strong verbal and written communication skills Ways to stand out from the crowd: Contributions and participation in the open source community. Familiarity with deep learning compilers. Familiarity with deep learning modeling trends. Background with CUDA Programming as well as Python.

Radiation Environmental Test Engineer (Mid-Level or Senior) Company: The Boeing Company Boeing Missile & Weapons Systems is seeking a Radiation Environmental Test Engineer (Mid-Level or Senior) to lead radiation and environmental test efforts supporting ICBM modernization at the Little Mountain Test Facility in Hill Air Force Base, UT. This hands-on role combines test design, execution, data analysis, and facility/test-stand maintenance. The position supports ongoing modernization efforts to enhance current test capabilities and new developing capabilities—identifying, designing, managing, and integration of new test stands, diagnostics, and data systems to meet evolving mission requirements. Position Responsibilities: Lead and execute complex radiation and environmental test machine design and facility integration Identify interface requirements, CDRLs, configuration control documentation, and change orders Design, specify, and integrate test hardware, sub-assemblies, fixtures, and instrumentation Assist in configuring, validating, and operating data acquisition systems and custom software (LabVIEW) for diagnostics and event capture Support pulse power and flash X-ray systems: theory, operation, diagnostics, and data capture Perform technical evaluation of subcontractors Basic Qualifications (Required Skills and Experience): Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement Level 3: 5&#43; years of related work experience and a bachelor’s degree or an equivalent combination of related work

NVIDIA is a global leader in high-speed computer vision, artificial intelligence (AI), and deep learning. Our team develops data engineering solutions that empower AI developers in autonomous vehicle (AV) domains to innovate quickly and effectively at scale. Are you ready to take on a senior technical role in building high-performance AI data pipelines? We seek an exceptional individual to design and optimize microservices and data pipelines to process massive volumes of AV data and enable seamless data mining and AI training. The ideal candidate will bring expertise in big data processing and distributed computing to create efficient solutions and overarching architectures for challenges such as video data curation, behavioral search, and AI dataset management. What you'll be doing: Scope and build tools, microservices, workflows, and distributed applications to accelerate data mining and AI training. Design and implement solutions for streaming, resilience, logging, security, authentication, workflow orchestration, and data management. Deploy AI models. Design and develop Retrieval-Augmented Generation (RAG) workflows enabling hybrid and agentic patterns. Analyze and operationalize complex distributed systems for speed-of-light performance. What we need to see: Experience developing high-performance, scalable software systems. MS with 6&#43; years, or BS (or equivalent experience) with 8&#43; years of relevant experience in Computer Science, Computer Engineering, or a related technical field. Strong programming skills in Python or Golang Proficiency in key technologies like Kubernetes, Helm, Hive, Parquet, SQL, vector databases, e.g., Milvus. Strong architectural skills with a proactive, problem-solving mentality. Experience in data mi

The DFP Engineer – Manufacturing role defines and implements the validation and screening of new silicon features within high‑volume manufacturing flows. You will translate product requirements into executable test methodologies, infrastructure, and detailed manufacturing test plans that ensure quality, yield, and efficiency at scale. This role sits at the intersection of multiple multi-functional teams to make manufacturing test an outstanding part of the overall codesign and DFP lifecycle. What you will be doing: Own end-to-end manufacturing test methodology across all test stages. Translate system specs and product POR into DFP requirements, test content, coverage, and flows. Define and maintain the DFP roadmap, including infrastructure and turning point planning. Partner multi-functionally to implement test content, debug hooks, and coverage improvements. Drive alignment on manufacturability, test time, binning strategies, and cost vs. coverage trade-offs. Embed testability requirements into design to enable robust screening and debug. Define data and analytics frameworks to support yield analysis and continuous improvement. Lead DFP documentation as the single source of truth and feed findings into future methodologies. What we need to see: MS in Electrical Engineering, Computer Engineering, or related field (or equivalent experience) 6&#43; years in silicon post‑silicon validation and/or high‑volume manufacturing test for complex SoCs, GPUs, CPUs, or similar. Hands‑on experience with test content bring‑up, limit setting, correlation to characterization, and yield/coverage optimization. Proficiency with scripting and data analysis (e.g., Python, MATLAB, R, SQL) for test data analytics, limit tuning, and yield/debug analysis. <

Build the infrastructure that keeps every NVIDIA chip aligned from first spec to final shipment. NVIDIA's Silicon Co-Design Group sits at the convergence of architecture, silicon, systems, and manufacturing. The System–Manufacturing Architecture (SMAC) team coordinates between system specifications and manufacturing test specifications from pre-silicon POR through production release across GPU, SoC, and CPU programs. When that alignment drifts, silicon faces the consequences: escapes, yield loss, and performance loss. We're hiring a Senior Manufacturing & System Co-Design Workflow Engineer to lead the methodology and infrastructure that maintains holistic, systematic alignment, at scale across the full portfolio. The strongest candidates in this role design the workflow before being asked to fix a program, and build the checks and automation that confirm alignment holds long after they've moved on to the next problem. What you’ll be doing: SMAC Workflow Methodology: Define manufacturing spec types, including schema and semantics, derived from system PORs and features. Own the methodology that governs how specification work gets structured, versioned, and validated across the program lifecycle. Production Python Pipelines & Automated Checks: Develop production-grade Python pipelines and automated checks that catch specification drift between system POR and manufacturing test programs ,ATE, SLT, BLT, L10&#43;, before silicon exposes the discrepancy. The goal is that misalignments surface in the workflow, not on the tester. E2E Program Integration & TPM Attestation: Wire SMAC work into the end-to-end program spine, milestones, gates, and artifacts, and define explicit TPM-driven attestation when checks lag. Alignment can't be assumed; it must be proven at every stage. Agent-Ready Tooling & CI Infrastructure: Integrate tooling into an agent-ready

NVIDIA is seeking elite ASIC Verification Engineers to verify the design and implementation of the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will help to build the high-performance processor elements that implement programmable compute and graphics functionality. What you'll be doing: As a key member of our ASIC Verification team, you will verify the design and implementation of the industry's leading GPUs You will be responsible for verification of the ASIC design, architecture, golden models and micro-architecture using advanced verification methodologies such as UVM Understand the design and implementation of your unit, define the verification scope, develop the verification infrastructure and verify the correctness of the design Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks What we need to see: Bachelors Degree in EE, CS or CE or equivalent experience 2&#43; years of relevant experience Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies Background with design and verification tools (VCS or equivalent simulation tools, debug tools like Verdi, GDB) Experience crafting test bench environments for unit and system level verification Strong background in System Verilog or similar HVL Expertise with C/C&#43;&#43; programmin

Abbott is a global healthcare leader that helps people live more fully at all stages of life. Our portfolio of life-changing technologies spans the spectrum of healthcare, with leading businesses and products in diagnostics, medical devices, nutritionals and branded generic medicines. Our 122,000 colleagues serve people in more than 160 countries. JOB DESCRIPTION: Job Title Associate Manufacturing Engineer About Abbott Abbott is a global healthcare leader, creating breakthrough science to improve people’s health. We’re always looking towards the future, anticipating changes in medical science and technology. Working at Abbott At Abbott, you can do work that matters, grow, and learn, care for yourself and family, be your true self and live a full life. You will have access to: Career development with an international company where you can grow the career you dream of. Health Insurance (starting on Day 1 of employment), Savings Plan (401K) with company match, Life insurance for you and your spouse/children, Short Term Disability, Long Term Disability, Education Assistance, Employee Assistance Program, Vacation, Sick, Personal Days. A company recognized as a great place to work in dozens of countries around the world and named one of the most admired companies in the world by Fortune. A company that is recognized as one of the best big companies to work for as well as a best place to work for diversity, working mothers, female executives, and scientists. The Opportunity This position works out of our Arecibo, PR location in the Cardiac Rhythm Management division and supports. As a global leader in Cardiac Rhythm Technologies, we focus on innovative technologies that can improve the way doctors treat people with heart arrhythmias, or irregular heartbeats.

NVIDIA's GPUs and SOCs are the world leaders in power, performance and efficiency. We are continually innovating to deliver new and creative, unusual solutions to extraordinary problems in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Package Layout Engineer who is committed to making a difference in the world through their contributions! This position will collaborate with Technical Package Lead and different design teams in the design and development of sophisticated, detailed layout of IC substrates for NVIDIA products. In addition, work with design teams to plan schedules, resolve costs, manufacturing, and electrical design issues. What you'll be doing: As part of a Layout team, you will collaborate to implement high speed/density ASIC packages. Perform substrate breakout patterns for ASIC packages. Optimize package pinout incorporating system level trade-offs of pins assignment. Help perform package routing, placement, stack-up, reference plane and power distribution using Cadence APD or SiP tool suite. Propose layout design trade-offs to the Technical Package Lead for resolution and implementation. Conduct design feasibility studies to evaluate the Package design goals for size, cost, and system performance. Develop symbols and CAD library databases using Cadence APD design tools Develop methodologies to improve layout productivity What we need to see: Hold a B.S. Electrical Engineering or equivalent experience 5&#43; years experience in PCB Layout of graphics cards, motherboards, line cards or other related technology. Experience with HDI designs is a plus Proven experience in substrate layout of wire bond and flip chip packages, preferred Significant background with Cadence AP

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. Our team builds AI-driven software systems for Circuit Design: combining automation algorithms, DL models and agentic workflows to accelerate end-to-end design automation. Come join this integral team in our Circuit Solutions Group! What you'll be doing: Work within a multi-functional team on various projects involving Pre-silicon and Post Silicon custom circuit design and related data, Circuit/Layout Optimization and Spice correlation Research and implement techniques on frontier solutions of electronic design automation. Build and innovate agentic AI solution for VLSI design problem. Responsible for analyzing the problem or datasets, raise and validate hypotheses, design and build models and algorithm until they reach the desired QOR. What we need to see: MS (or equivalent experience) with 3&#43; years’ experience or PhD with 1&#43; years’ experience in Electrical/Computer Engineering degree Experience in the following fields is a strict requirement for this role: Combinatorial Optimization, Agentic AI and large language models, Machine Learning for Chip Design & EDA Experience in Algorithms/Data Structures/

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. About Fab 4 Wet Process Operations Fab 4 Wet Process Operations supports the safe, efficient, and high-quality movement of wafers through the Wet Process area. Our team works closely with peer manufacturing areas, Process teams, Equipment teams, and many other organizations to supervise fab performance, manage production risks, optimize cycle time, and drive execution against move targets. Through real-time decision making and continuous improvement, we help ensure the fab meets customer and business commitments. Position Summary The Shift Manufacturing Engineer (ME) is responsible for driving daily fab performance within the assigned area. This role partners closely with Manufacturing Technicians, Shift Lead Engineers, Process Engineers, and Operations teams to achieve wafer move targets, optimize cycle time, respond to quality concerns, and maintain efficient workflow through the manufacturing line. Working on a 12-hour compressed workweek schedule, this position provides real-time operational leadership by identifying manufacturing constraints, supervising material flow, supporting production decisions, and driving actions needed to meet weekly wafer movement and wafer-on-hand objectives. Responsibilities: Supervise wafer movement performance by DID, process step, and operational targets. Identify manufacturing gaps, WIP imbalances, bottlenecks, and workflow disruptions. Develop and implement plans to close gaps and achieve weekly move and wafer-on-hand commitments.</l