Engineer Senior in Arizona

Packaging Module Development Engineer — US, Arizona, Phoenix. Apply via Workday.

Packaging Research and Development Engineer — US, Arizona, Phoenix. Apply via Workday.

Job Details: Job Description: As a Packaging Module Development Engineer, you will play a pivotal role in the development and optimization of Intel's assembly media and collaterals. Your daily work will involve designing innovative solutions to improve media and collateral reliability, manufacturability, and cost efficiency. Your contributions will directly support Intel's cutting-edge assembly packaging technology roadmap, driving advancements in semiconductor manufacturing processes. Business Group You will be part of Intel Corporation's Media Development organization, a team dedicated to advancing packaging technologies and manufacturing processes. This group operates at the forefront of innovation, enabling high-performance products and driving Intel's leadership in the semiconductor industry. By joining this collaborative environment, you will contribute to Intel's broader goals of delivering transformative technology solutions. Key Responsibilities Develop and optimize media and collaterals to meet quality, reliability, cost, yield, and productivity targets. Design and implement new media and collateral solutions, leveraging statistical methods like Design of Experiments (DOE) and Statistical Process Control (SPC). Conduct evaluations of media and collaterals under simulated field conditions, including tests for heat, humidity, temperature cycling, and dynamic forces. Lead initiatives to identify and mitigate media and collateral quality and reliability risks, utilizing innovative tools and methods. Provide technical consultation on media and collateral challenges and deliver solutions that align with operational and technology milestones. Document technical improvements and innovations through research papers and presentations. <p styl

Job Details: Job Description: Ocotillo Technology Fabrication Yield is looking for Integration Technicians with a strong computing background and capabilities to support all Ocotillo Technology Fabrication platforms and beyond technologies. The candidate will work closely with a team of Integration Technicians to execute experiments/pilots, develop process flows and lot plans for new product introductions, and support taskforces. As a Process Integration and Yield Technician, you will play a critical role in Intel's high-tech manufacturing process, your contributions will directly impact Intel's innovation, enabling the delivery of advanced technologies that power the future of computing. This is an exciting opportunity to grow your technical expertise, work alongside engineering teams, and be part of a collaborative environment where your skills make a tangible difference. The Process Integration and Yield Technician will be responsible for but not limited to: Sustaining factory floors with lot plan/operation/route/process flow checks/rework/critical queue time edits, shipping errors, automation errors, process flow adjustments, wafer shipments, and scraps. Delivering lot plan owner training to the Ocotillo Technology Fabrication organization Collaborate with integration engineers to gather data needed for lot disposition Respond to and contain discrepant material in the fab Conduct engineering tests and detailed experimental testing to collect data or assist in research work related to integration, process, and yield. Provide pilot lot set up and cross site shipment support. Process change support and implementation via global flow changes, global route changes, and lot conversions The ideal candidate should exhibit the following behavioral traits: Self-starter an

Job Details: Job Description: As one of the world's largest semiconductor manufacturers, Intel is committed to advancing every aspect of semiconductor technology, from process development and manufacturing to advanced packaging and reliability characterization. Employees within Intel Foundry are part of a global network spanning technology development, manufacturing, assembly, test, and quality organizations across both front-end silicon and advanced packaging facilities. You will join the Foundry Lab Network (FLN), a key organization within Foundry Quality, Reliability, and Labs (FQRL), located at Intel's growing Chandler, Arizona site. This site serves as the technology development hub for Intel's most advanced packaging technologies, including Hybrid Bond Interconnect (HBI), Embedded Multi-die Interconnect Bridge (EMIB-T), glass substrates, Foveros, and future advanced packaging innovations. FLN is actively expanding its laboratory capabilities and capacity to support Intel Foundry's roadmap, enabling faster technology qualification and accelerating development cycles through Quick Turn Monitoring (QTM) solutions that significantly reduce time-to-data. As the Stress Test and Reliability (STaR) Back-End Laboratory Manager, you will play a critical leadership role within FLN. You will partner closely with Packaging Technology Development, Quality and Reliability, and Failure Analysis teams to establish and enhance laboratory capabilities that support qualification and certification of next-generation packaging technologies and products. This position offers a unique combination of people leadership, technical problem solving, and organizational strategy. You will lead a team of 7-10 talented engineers, spearhead cross-functional efforts to resolve complex reliability and technology challenges, drive strong quality and operati