Junior It Systems Engineer in United States

About the Team The Capital Markets team develops the financing strategy, solutions, and partnerships needed to support our expanding global AI infrastructure platform and long-term investment plans. About the Role We’re looking for a senior structured finance leader to create immediate execution leverage for a growing capital markets function. In this role, you’ll take broad financing objectives, such as raising a large pool of capital from a defined set of counterparties, and independently turn them into well-run transaction processes. You’ll lead complex financings from strategy through close, manage counterparties and advisors, and bring sound judgment to capital structure, risk allocation, process design, and execution. This is a hands-on role for someone who is still close to the details, not a purely senior relationship manager. Your work will allow the team lead to spend less time in day-to-day execution and more time building the broader capital markets organization. In this role, you will: Lead large, complex financing processes from initial structuring through diligence, negotiation, documentation, and closing. Translate broad capital-raising objectives into executable financing plans, timelines, work streams, and counterparty strategies. Manage lenders, investors, advisors, counsel, and internal stakeholders across high-stakes transactions. Provide oversight on financial structuring, modeling, diligence, risk allocation, and transaction documentation. Make clear recommendations on financing strategy, counterparty selection, process design, and tradeoffs. Operate effectively in a small, high-impact team without relying on a large analyst or associate bench. Help build repeatable internal processes for a financing function that is still scaling. Coach and develop more junior transaction professionals. You might thrive in this role if you have: 8-15 years of experience executing structured finance, project finance, infrastructure finance, digital infrastruct

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale. This is a senior, hands-on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure, physical design convergence, bring-up, and production readiness. You will plan and oversee the work of junior engineers and help drive and develop productive engineering relationships with external partners and help manage partner execution. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic as well as off-chip protocol bridges and interfaces. Drive third party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and de