Production Operator in United States

About the Team The Privacy Engineering Team at OpenAI is committed to integrating privacy as a foundational element in OpenAI's mission of advancing Artificial General Intelligence (AGI). Our focus is on all OpenAI products and systems handling user data, striving to uphold the highest standards of data privacy and security. We build essential production services, develop novel privacy-preserving techniques, and equip cross-functional engineering and research partners with the necessary tools to ensure responsible data use. Our approach to prioritizing responsible data use is integral to OpenAI's mission of safely introducing AGI that offers widespread benefits. About the Role As a part of the Privacy Engineering Team, you will work on the frontlines of safeguarding user data while ensuring the usability and efficiency of our AI systems. You will help us understand and implement the latest research in privacy-enhancing technologies such as differential privacy, federated learning, and data memorization. Moreover, you will focus on investigating the interaction between privacy and machine learning, developing innovative techniques to improve data anonymization, and preventing model inversion and membership inference attacks. This position is located in San Francisco. Relocation assistance is available. In this role, you will: Design and prototype privacy-preserving machine-learning algorithms (e.g., differential privacy, secure aggregation, federated learning) that can be deployed at OpenAI scale. Measure and strengthen model robustness against privacy attacks such as membership inference, model inversion, and data memorization leaks—balancing utility with provable guarantees. Develop internal libraries, evaluation suites, and documentation that make cutting-edge privacy techniques accessible to engineering and research teams. Lead deep-dive investigations into the privacy–performance trade-offs of large models, publishing insights that inform model-training and prod

About the Team The Developer Experience team at OpenAI has a singular focus: empowering developers globally. Our mission is to provide every developer and startup on the planet with the most delightful and seamless experience to integrate AI into their applications and products. We ensure developers have the tools, resources, and support they need to unlock AI’s full potential. We create inspiring demos, developer tools, sample applications, and technical content that show developers how to build with Codex and frontier models like GPT-5.6, GPT-Live, and GPT-Image-2 to create powerful agents and AI-native applications. We collaborate closely with product, engineering, research, and GTM teams to ensure the developer journey, from onboarding with Codex to first API call to production deployment, is seamless, effective, and delightful. About the Role As a Developer Experience Engineer, you will create compelling technical content, developer tools, and sample applications designed to inspire developers and enable them to succeed with Codex and OpenAI’s APIs and products for developers. You will engage with developers and technical founders, demonstrating best practices and building innovative applications powered by frontier models, multimodal capabilities, and tools like Codex. We’re looking for people who combine strong technical skills, creativity, and a passion for engaging with and empowering developers. In this role, you will: Develop demos and sample applications that showcase best practices for building with Codex, frontier models, multimodal capabilities, and agents. Create high-quality technical content—including tutorials, blog posts, videos, and code samples—to educate and inspire the developer community about our models, APIs, and Codex. Actively engage with and foster a vibrant local and global developer ecosystem around OpenAI’s platform and products. Represent OpenAI at developer events and online, serving as a knowledgeable and approachable advocate for

About the Team We are building general-purpose robotics. In the short term, we are focused on robots to support skilled workers to build our future infrastructure. In the long term, we imagine everyone having a personal robot doing anything they need. Progress is rapid, and based on a foundation of co-design between robotics hardware and ML research. About the Role As a Firmware Engineer, you will define and drive the architecture of embedded systems for next-generation hardware products. You will own foundational firmware decisions across real-time execution, device bring-up, hardware interfaces, fault handling, safety mechanisms, and production readiness. We’re looking for someone with deep experience building safety-critical or high-consequence systems, where failures can have meaningful consequences. You should be comfortable reasoning about risk, designing for diagnosability and graceful degradation, and creating engineering practices that raise the reliability bar for the entire team. You should also be unusually good at moving fast. Sometimes the right answer is a carefully reviewed architecture that will endure for years; sometimes it is getting a rough-but-useful prototype working by the end of the afternoon so the team can learn something concrete tomorrow. We value engineers who know the difference, make that call well, and can operate credibly in both modes. You will be both a technical leader and a hands-on builder: setting direction, reviewing critical designs, unblocking the hardest problems, and writing production firmware when it matters most. Our embedded stack uses a lot of Rust. Extensive experience in the language is a big help! This role is based in San Francisco, CA. This role will be expected to be in office 4 days per week and offer relocation assistance to new employees. In this role, you will: Rapidly bring up new hardware and set execution pace for the team. Lead firmware architecture for embedded systems spanning boot, RTOS/runtime behav

About the Team IT Systems Operations serves as the operational control layer connecting Security, Engineering, and Employee Technology platforms. The team ensures employee-facing systems, identity workflows, and enterprise applications operate in a predictable, governed, and continuously reliable manner as the organization scales. Beyond implementation, the team establishes structured operating patterns that ensure platform changes, access models, integrations, and lifecycle workflows evolve safely and consistently across the enterprise environment. About the Role This role acts as an operational owner for identity-connected enterprise SaaS platforms and system change controls supporting OpenAI’s compliance requirements. The engineer will be responsible for ensuring that production configuration, access models, and platform changes remain compliant, auditable, and consistently operated through defined controls. You will own and operationalize controlled system and workflow changes across identity platforms, SaaS applications, collaboration tooling, and enterprise infrastructure. You will partner closely with Security, Platform Engineering, and IT Support Operations to: Ensure identity and access workflows behave consistently across systems Implement structured rollout and configuration practices for enterprise applications Improve visibility and traceability of system changes impacting employee workflows Translate operational requirements into durable automation and policy-aligned implementations Success in this role requires not only strong engineering capability, but also sound operational judgment, disciplined documentation practices, and effective cross-functional collaboration. In this role, you will: Enterprise SaaS & Identity Platform Ownership Own administration and operational stewardship of enterprise SaaS and identity-connected platforms, ensuring configuration integrity, access governance, and compliance with defined control requirements. Own onboard

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role OpenAI's Hardware organization builds supercompute platforms from silicon and boards to full rack-scale systems to power advanced AI workloads. This role owns end-to-end quality for high-speed interconnect hardware across the product lifecycle: early design influence, supplier/contract manufacturer readiness, qualification, ramp, and fleet quality in lab and data center environments. You will be the quality lead for advanced interconnect components and assemblies, including high-speed copper cables, cable cartridges, patch panels, backplane/cable-backplane solutions, high-speed connectors, and related electro-mechanical interfaces. You will partner closely with electrical, mechanical, SI/PI, systems, reliability, operations, and external vendors to prevent escapes and drive rapid, data-driven containment and corrective action. In this role you will: Own quality for advanced interconnect components and assemblies: high-speed connectors, high-speed copper cables, cable cartridges (e.g., cable cassette style assemblies), patch panels & optics, and backplane/cable-backplane interconnect solutions. Drive quality-by-design: participate in design reviews, DFM/DFx, tolerance stacks, material and plating selections, connector mating strategy, strain relief, and assembly methods to reduce variation and field failures. Define and track quality and reliability metrics (DPPM, yield, escapes, RMA/FRACAS trends, Cpk/Ppk where applicable) for interconnects across NPI and m

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role You will develop and evolve the tooling ecosystem that hardware engineers rely on every day — from hardware compilers and IR transformations to simulation, debugging, and automation infrastructure. The work spans software engineering, compiler concepts, and practical hardware workflows, with direct impact on how quickly and effectively we design next-generation AI systems. You’ll collaborate closely with architects, RTL designers, and verification engineers to translate real engineering friction into durable, scalable tooling solutions. In this role you will: Build and improve the software tooling that makes hardware teams faster: compilation, IR transforms, RTL generation, simulation, debug, and automation. Extend and integrate hardware compiler stacks (frontends, IR passes, lowering, scheduling, codegen to Verilog/SystemVerilog) and connect them to real design workflows. Improve developer experience and reliability: reproducible builds, better error messages, faster iteration loops, and dependable CI and regression infrastructure. Work closely with designers and verification engineers to turn real pain points into durable tools. Dive into RTL when needed: read and reason about Verilog/SystemVerilog to debug issues, validate tool output, and improve debuggability. Be willing to go all the way down the stack when necessary, including gate-level views, synthesis results, and implementation artifacts. Help enable PPA optimization loops by building analysis and au

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are seeking a Operations Program Manager (OPM) to serve as the single-threaded operational leader for new hardware introductions (NPI) and production ramps across OpenAI’s AI infrastructure systems. This role combines hands-on execution with strategic ownership. You will be responsible for defining the operating model, aligning cross-functional stakeholders, setting the critical path, making informed tradeoffs, escalating decisively, and ensuring hardware programs deliver on schedule, quality, cost, and scalability. Success in this role requires comfort operating in ambiguity, influencing without authority, and driving alignment across internal teams and external partners—while keeping eyes firmly on long-term system scalability and repeatability. In this role, you will: Strategic & Leadership Ownership Act as the single-threaded owner for operational readiness across NPI and ramp, accountable for outcomes from early bring-up through sustained production Translate OpenAI’s infrastructure strategy and engineering objectives into clear operating plans, execution priorities, and decision frameworks Drive alignment across Engineering, Operations, Strategic Sourcing, Finance, Capacity Planning, and Executive stakeholders by framing tradeoffs, risks, and recommendations Proactively identify inflection points where decisions or investments are required to protect long-term scale, reliability, or cost targets Influence operational strategy with manufacturing par

About the Team OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI. About the Role As an Engineer on our hardware optimization and co-design team, you will co-design future hardware from different vendors for programmability and performance. You will work with our kernel, compiler and machine learning engineers to understand their unique needs related to ML techniques, algorithms, numerical approximations, programming expressivity, and compiler optimizations. You will evangelize these constraints with various vendors to develop and influence future hardware architectures towards efficient training and inference on our models. If you are excited about efficiently distributing a large language model across devices, dealing with and optimizing system-wide/rack-wide networking bottlenecks and eventually tailoring the compute pipe and memory hierarchy of the hardware platform, simulating workloads at different abstractions and working closely with our partners, this is the perfect opportunity! This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. Key Responsibilities Co-design future hardware for programmability and performance with our hardware vendors Assist hardware vendors in developing optimal kernels and add support for it in our compiler Develop performance estimates for critical kernels for different hardware configurations and drive decisions on compute core and memory h

About the Team The AI Architect team partners with organizations to turn OpenAI's most capable models into meaningful, real-world impact. We work with customers across industries and digital-native businesses to identify where AI can create value, design secure and scalable solutions, and help those solutions move from early exploration into sustained production adoption. The team brings together technical strategy, customer partnership, and practical deployment expertise, working closely with Sales, Product, Engineering, Research, and specialist delivery teams. About the Role As an AI Architect, you will be the senior technical owner for a named portfolio of customers and the primary technical counterpart to their leadership teams. You will act as the “CTO of your book of business”, shaping each customer's AI strategy and guiding their journey from pre-sales discovery and solution evaluation through deployment, adoption, and measurable business impact. You will own the technical account plan across ChatGPT Enterprise, the OpenAI API, Codex, and other agentic AI solutions. In partnership with the Account Director, you will translate business priorities into a focused use-case portfolio, an actionable adoption roadmap, and a clear path to durable customer value and growth. The Account Director owns commercial strategy; you own the technical strategy, customer journey, and path to production value. You will remain accountable for the technical outcome while bringing in the right specialists across deployment, implementation, enablement, security, product, and partners to provide deeper expertise and execute work where needed. This role calls for strong industry fluency, sound architectural judgment, and the ability to move confidently between executive strategy and hands-on technical conversations. In this role, you will: Serve as the primary technical advisor and long-term technical relationship owner for a named portfolio of existing customers and pre-sales prospect

About the Team The AI Architect team partners with organizations to turn OpenAI's most capable models into meaningful, real-world impact. We work with customers across industries and digital-native businesses to identify where AI can create value, design secure and scalable solutions, and help those solutions move from early exploration into sustained production adoption. The team brings together technical strategy, customer partnership, and practical deployment expertise, working closely with Sales, Product, Engineering, Research, and specialist delivery teams. About the Role As an AI Architect, you will be the senior technical owner for a named portfolio of customers and the primary technical counterpart to their leadership teams. You will act as the “CTO of your book of business”, shaping each customer's AI strategy and guiding their journey from pre-sales discovery and solution evaluation through deployment, adoption, and measurable business impact. You will own the technical account plan across ChatGPT Enterprise, the OpenAI API, Codex, and other agentic AI solutions. In partnership with the Account Director, you will translate business priorities into a focused use-case portfolio, an actionable adoption roadmap, and a clear path to durable customer value and growth. The Account Director owns commercial strategy; you own the technical strategy, customer journey, and path to production value. You will remain accountable for the technical outcome while bringing in the right specialists across deployment, implementation, enablement, security, product, and partners to provide deeper expertise and execute work where needed. This role calls for strong industry fluency, sound architectural judgment, and the ability to move confidently between executive strategy and hands-on technical conversations. In this role, you will: Serve as the primary technical advisor and long-term technical relationship owner for a named portfolio of existing customers and pre-sales prospect

About the Team The Consumer Products team at OpenAI builds end-to-end hardware and software systems that bring AI into the physical world. We work at the intersection of custom silicon, embedded systems, operating systems, and cloud services to deliver reliable, production-ready devices at scale. Within Consumer Products, the camera stack is a critical sensing component. The team partners closely with electrical engineering, silicon vendors, systems, and higher-level perception and product teams to bring up new hardware, stabilize capture pipelines, and ensure camera systems are robust, debuggable, and ready for real-world deployment. This work spans early prototypes through production, with a strong emphasis on correctness, repeatability, and long-term reliability. About the Role As a Camera Firmware Engineer, you will own low-level camera enablement on custom hardware—from early board bring-up through stable production capture. You will develop and maintain the firmware and software that makes camera sensors reliable, controllable, and debuggable, forming the foundation for higher-level camera pipelines and product features. This role is highly hands-on and systems-oriented. You will work close to the hardware, diagnose real-world timing and integration issues, and build tooling that accelerates iteration across the entire camera stack. This role is based in San Francisco, CA. We follow a hybrid work model with four days per week in the office and offer relocation assistance to new employees. In This Role, You Will Bring up new camera sensors and modules on prototype and production boards, including link stability, sensor control, and correct power, reset, and clock sequencing. Develop and maintain low-level camera software, including sensor drivers, board configuration, and camera subsystem integration across hardware revisions. Enable and validate core capture paths for development and production, including RAW capture for debugging, still capture, and hardware-

About the Team The Software Engineering Firmware team builds reliable, high-performance systems on custom hardware. We work closely with hardware engineers to design, optimize, and ship software that bridges cutting-edge devices and real-world constraints like memory, power, and latency. Our work spans early prototyping through product launch, ensuring that our embedded platforms are robust, efficient, and production-ready. About the Role As a Firmware Engineer , you will design, implement, and debug software for embedded devices. You’ll own low-level bring-up, write production C/C++ code, and partner closely with hardware teams to deliver reliable, high-performance systems. We’re looking for engineers with deep embedded expertise, strong debugging skills, and a passion for building systems that perform under real-world conditions. This role is based in San Francisco, CA . We use a hybrid work model of four days in the office per week and offer relocation assistance to new employees. In this role, you will: Design, implement, and debug software for embedded devices. Contribute to defining software requirements, interfaces, and test plans. Bring up and debug new boards. Analyze performance, memory, and power profiles and implement optimizations. Investigate field issues, perform root-cause analysis, and deliver robust fixes. Foster good software engineering practices. You might thrive in this role if you: Have deep experience shipping embedded systems (around 10+ years). Are proficient in C and C++. Are familiar with embedded toolchains, operating systems, and debugging tools. Have experience with both rapid prototyping and scalable product development. (Nice to have) Have experience with Zephyr RTOS. (Nice to have) Have worked with networking/wireless stacks (BLE, Wi-Fi). (Nice to have) Have experience with robotic system bring-up or Linux kernel development. About OpenAI OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose arti

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. Role summary We are seeking a Networking Operating System Firmware Engineer to help bootstrap and scale the switching layer of our AI supercomputers. In this role, you will build and maintain custom NOS images from scratch, using open source components from SONiC, SAI, FRR, and related networking stacks while working across the Linux kernel, switch ASIC SAI/SDKs, platform drivers, control-plane services, and orchestration layers. This is a software engineering role that requires a deep understanding of networking, NOS internals, switch hardware, and production systems. You will design, implement, test, and debug production NOS software across platform drivers, routing and control-plane state, ASIC programming, observability, and fleet integration. The engineer in this role should be able to work through ambiguous, open-ended technical problems and drive feature development across software, hardware, and vendor boundaries. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will Design, develop, and maintain custom NOS images for large-scale AI fabrics, using open source components from SONiC, FRR, and related networking stacks. Integrate, build and configure Linux kernel components, device drivers, switch ASIC SDKs, and SAI layers. Bring up new switch platforms, including thermal and fan control, power monitoring, transceiver management, watchdogs, OSFP CMIS, L

About the Team The Release Engineer team is responsible for building and maintaining the systems that power software delivery—from CI/CD pipelines and artifact management to release automation and fleet telemetry. We ensure software across bootloaders, firmware, operating systems, and cloud services is built reproducibly, validated rigorously, and released safely at scale. About the Role As a Release Engineer, you’ll design, build, and operate release infrastructure that enables reliable, secure, and traceable software delivery across complex multi-component systems. You’ll partner closely with embedded, cloud, and QA teams to ensure that every build—from development to OTA deployment—is fast, verifiable, and production-ready. We’re looking for engineers who take pride in automation, build reproducibility, and system reliability—and who enjoy building the connective tissue that allows hardware and software to ship together seamlessly. This role is based in San Francisco, CA. We use a hybrid work model of four days in the office per week and offer relocation assistance to new employees. In this role, you will: Design and operate CI/CD pipelines for multi-component builds (bootloader, firmware, OS images, backend, companion apps) using hermetic toolchains. Define versioning and branching strategies; automate promotions, changelogs, and artifact retention. Integrate unit, integration, and hardware-in-the-loop (HIL) test results; quarantine flaky tests, auto-bisect failures, and block unsafe promotions. Build A/B OTA update flows with verity and health checks; run staged rollouts and canaries; implement safe rollback and roll-forward strategies. Implement code signing for binaries and firmware, generate SBOMs, run vulnerability scanning, and attach build attestations and provenance. Manage dashboards and alerts for build health, promotion latency, failure rates, and fleet update telemetry. You might thrive in this role if you: Have experience building and operating buil

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for an embedded engineer to help build firmware and associated modeling software for OpenAI’s in house AI accelerator. This role involves designing and developing drivers and functional models for a large array of HW components, writing high throughput and low latency firmware code, investigating bring-up and production issues. Responsibilities Design and implement drivers for hardware peripherals, including those related to AI chips. Design and implement functional software models to simulate SoC uncore logic and enable FW testing against the model Design and implement low-latency and high throughput embedded SW to manage HW resources. Work with adjacent software and hardware teams to implement requirements, debug issues and shape future generations of the hardware. Collaborate with vendors to integrate their technologies within our systems. Bring up and debug firmware/driver on new platforms. Come up with processes and debug issues raised in the field. Set up monitoring, integration testing and diagnostics tools. Qualifications 5+ years of experience working in embedded SW space. Ability to thrive in ambiguity and learn new technologies. Strong programming skills in C/C++ and/or Rust. Experience developing high throughput, low latency and multi-threaded code. Experience working with real time operating systems (RTOS). Experience developing hardware drivers and working with hardware Experience with HW/SW co-design Knowledge of common embedded pr