Senior Design Quality Engineer in United States

Work Flexibility: Hybrid or Onsite Stryker is hiring a Senior Quality Engineer to join our Neurovascular division. This is a hybrid r ole based in Fremont, CA or Salt Lake City, UT . As the Senior Design Quality Engineer , you will be actively involved in Product Risk Management, Post Market Surveillance, Design Control and Product Quality Improvement. You will be involved in a fast-paced mix of short design change efforts and will be responsible for product risk management and adherence to design control requirements throughout the product lifecycle. You will be responsible for ensuring that post market data and feedback is channeled into the risk management system throughout the product lifecycle. You will make regular use of problem-solving tools and statistical analysis to analyze and trend data and provide quality input into technical investigations, perform test method development and validation, design verification, risk assessment and design reviews. You will be responsible for supporting product testing and failure analysis, writing protocols and reports, creating and maintaining risk files and assessing the impact of necessary changes to our products. You will lead initiatives to increase sales and improve the customer experience of our devices. Neurovascular (NV) products push the boundaries of technology to meet ever increasing product performance requirements, making the goal of assessing and demonstrating, safety, performance and compliance an exciting challenge. What You Will Do Develop qualification plans, protocols, and reports for new products, existing products, components, and subassemblies. Execute product testing, inspection, verification, and validation activities to support design and quality objectives. Perform failure investigations and root cause anal

Work Flexibility: Hybrid or Onsite Stryker is hiring a Senior Quality Engineer to join our Neurovascular division. This is a hybrid r ole based in Fremont, CA . As the Senior Design Quality Engineer , you will be actively involved in Product Risk Management, Post Market Surveillance, Design Control and Product Quality Improvement. You will be involved in a fast-paced mix of short design change efforts and will be responsible for product risk management and adherence to design control requirements throughout the product lifecycle. You will be responsible for ensuring that post market data and feedback is channeled into the risk management system throughout the product lifecycle. You will make regular use of problem-solving tools and statistical analysis to analyze and trend data and provide quality input into technical investigations, perform test method development and validation, design verification, risk assessment and design reviews. You will be responsible for supporting product testing and failure analysis, writing protocols and reports, creating and maintaining risk files and assessing the impact of necessary changes to our products. You will lead initiatives to increase sales and improve the customer experience of our devices. Neurovascular (NV) products push the boundaries of technology to meet ever increasing product performance requirements, making the goal of assessing and demonstrating, safety, performance and compliance an exciting challenge. What You Will Do Develop qualification plans, protocols, and reports for new products, existing products, components, and subassemblies. Execute product testing, inspection, verification, and validation activities to suppor

Job Title Senior Supplier Quality Engineer Job Description The Senior Supplier Quality Engineer ensures supplier quality, compliance, and process capability across sustaining activities within Philips’ Image Guided Therapy Devices business. Your role: Serves as the primary Supplier Quality Engineering point of contact for the Colorado Springs, CO facility, providing on-site support ensuring timely alignment with site Quality, Manufacturing, R&D, Sustaining Engineering, Procurement, and supplier stakeholders. Leads and owns MSA, PFMEA, Control Plan, SPC, PV&V, FAI, IQ/OQ/PQ, and related APQP / PPAP activities to ensure supplier process capability, validation readiness, and compliance with quality requirements. Leads APQP / PPAP execution for supplier transfers, supplier changes, SICRs, and sustaining projects supporting the Fremont, CA manufacturing facility. Facilitates Design for Excellence collaboration between R&D, Sustaining Engineering, Manufacturing, and suppliers to improve design quality, manufacturability, supplier process robustness, and long-term product performance. Ensures Critical to Quality characteristics are clearly defined, flowed down to suppliers, validated through appropriate controls, and maintained throughout production. Leads supplier audits, including initial qualification, for-cause, and follow-up audits, to assess supplier compliance with applicable quality system requirements, regulatory expectations, process controls, and supplier agreement obligations. Leads supplier qualification activities for addition to the Approved Supplier List, including supplier capability assessment, quality system maturity evaluation, technical readiness, risk classification, approval documentation, and onboarding completion. Leads supplier-related non-conformance investigations, including defect

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Sr Design Engineer, you will work on design, simulation, and validation of next ‑ generation High ‑ Bandwidth Memory (HBM) architectures and circuit blocks. HBM requires advanced DRAM design knowledge combined with deep understanding of 3D stacked architecture, TSV signaling, wide I/O interfaces, PHY timing, power integrity, and system co ‑ optimization with GPUs/accelerators. This role sits at the intersection of DRAM design and high ‑ performance computing, enabling future AI/ML, HPC, and advanced graphics products. In this position, you will collaborate with Micron’s various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction.

The way products get built is changing. Agents write a growing share of shipped interfaces, designers work in code, and a design system's output is bigger than a component library. At Datadog we're redefining ours for that world, and evolving how the product looks and feels at the same time. DRUIDS is the design system behind every Datadog surface, used daily by more than a hundred designers and thousands of engineers across thirty-plus products. You'll lead the team that owns it: designers and design engineers who set the system's direction, hold the quality bar for what ships, and build the tools that make designing in code the default way to work. The team partners closely with product designers, frontend engineers and PMs across the company. This is a hands-on leadership role in a technical, engineering-forward company. You'll be expected to have a point of view and defend it, to be the person the design org asks about quality, and to make the call when work isn't good enough yet. Much of what a design system should be right now hasn't been settled — here or anywhere else. If you're a designer who never stopped making things, and you'd rather decide what a system should be than maintain one that already exists, this is the role. At Datadog, we place value in our office culture - the relationships and collaboration it builds and the creativity it brings to the table. We operate as a hybrid workplace to ensure our Datadogs can create a work-life harmony that best fits them. What You'll Do Lead the team and set its direction Decide what DRUIDS owns, what it ships, and what stays with product teams. Own where the system goes next. Have a view on what a design system should be, and argue for it. Turn direction into a roadmap, and work with partners on what gets built and when. Coach the designers and design engineers on your team, be clear about what each person owns, and hire as the team grows. Own craft and quality Own the craft and quality of components, patterns,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron is seeking a highly motivated and experienced Technical Staff Member to join our Quality Engineering team in Boise, ID. Your role will be crucial in ensuring the reliability and quality of wafers shipped from our Boise manufacturing site! Summary The Product Quality and Reliability team ensures Micron delivers high-quality, reliable semiconductor solutions that meet customer expectations and business objectives. The team partners across product engineering, design, technology development, manufacturing, and reliability organizations to identify risks, solve complex technical challenges, and drive continuous improvements in product performance, yield, and customer satisfaction! Position Overview As a Senior Product Quality and Reliability Engineer, you will be a technical leader. You will drive product excellence in quality, dependability, and yield across advanced semiconductor technologies. You will lead complex technical investigations, influence product and technology decisions, and develop innovative approaches that strengthen quality systems and business outcomes. This role provides an opportunity to have broad interpersonal impact through technical leadership, multi-functional teamwork, and strategic problem-solving. Responsibilities Lead complex investigations involving yield excursions, product deviations, and quality issues, driving root cause identification, containment actions, and sustainable corrective solutions Define product quality and reliability moni

Every day, tens of millions of people come to Roblox to explore, create, play, learn, and connect with friends in 3D immersive digital experiences– all created by our global community of developers and creators. At Roblox, we’re building the tools and platform that empower our community to bring any experience that they can imagine to life. Our vision is to reimagine the way people come together, from anywhere in the world, and on any device. We’re on a mission to connect a billion people with optimism and civility, and looking for amazing talent to help us get there. A career at Roblox means you’ll be working to shape the future of human interaction, solving unique technical challenges at scale, and helping to create safer, more civil shared experiences for everyone. The Consumer Apps Consoles team owns the console app foundation that makes Roblox feel fast, fluid, and reliable for millions of players and is dedicated to delivering superior performance, reliability, and user experience on PlayStation and Xbox. As a Senior Software Engineer on the Consoles team, you'll be a driving technical force — leading complex client work end-to-end, raising the quality bar across our codebase, and partnering closely with product, design, and platform teams to ship experiences that are polished and performant at scale. You Will: Shape & improve the PlayStation and Xbox experience that millions of players see every day Translate ambiguous product ideas into well-scoped, high-quality engineering plans in close partnership with product, design, and data science. Raise the engineering bar through rigorous code review, proactive mentorship of junior engineers, and the standards you set in your own code. Drive platform-level investments that benefit the broader engineering organization. Work with our Xbox and PlayStation counterparts to ensure feature parity and platform-specific excellence. You Have: 5+ years of experience building and shipping client software, with

Every day, tens of millions of people come to Roblox to explore, create, play, learn, and connect with friends in 3D immersive digital experiences– all created by our global community of developers and creators. At Roblox, we’re building the tools and platform that empower our community to bring any experience that they can imagine to life. Our vision is to reimagine the way people come together, from anywhere in the world, and on any device. We’re on a mission to connect a billion people with optimism and civility, and looking for amazing talent to help us get there. A career at Roblox means you’ll be working to shape the future of human interaction, solving unique technical challenges at scale, and helping to create safer, more civil shared experiences for everyone. As a Senior QA Engineer, you will be the first dedicated QA hire for the Safety Engineering Group, which is responsible for building the infrastructure and policies that make Roblox the safest online community in the world. You will report to the QA Engineering Manager for Universal Apps and collaborate across the Safety organization to own end-to-end test strategies for high-stakes, 24/7 incident response systems and parent-facing safety features. This role is a unique opportunity to shape the quality culture of a company-level mandate from the ground up. You will: Partner with Engineering and Product to define and maintain comprehensive, risk-based test coverage for Safety features and systems. Own the end-to-end test strategy for Safety initiatives, including functional, regression, integration, and edge-case validation. Leverage and expand internal automation frameworks to automate critical user flows and drive API-first validation strategies. Identify high-impact automation opportunities and incorporate industry best practices to design robust, abuse-resistant test scenarios. Develop, track, and report on quality metrics (e.g., defect trends, coverage gaps) to proactively surface relea

At Vanta, our mission is to help businesses earn and prove trust. We believe that security should be monitored and verified continuously, and we empower companies to practice better security and prove it with ease. Vanta has a kind and talented team, and while some have prior security experience, many have been successful at Vanta without it. Senior Software Engineer, Trust (TPRM) - Job Description As a Senior Software Engineer on Vanta's Trust TPRM team, you'll build the full-stack product experiences and underlying data infrastructure that help enterprises manage vendor risk at scale — working across teams focused on vendor lifecycle management and vendor monitoring. Vanta's Trust TPRM (Third-Party Risk Management) team is building the products that make vendor risk management seamless for security and procurement teams. From vendor onboarding and lifecycle management to continuous monitoring and procurement integrations, we're creating the platform that helps Vanta customers understand, track, and mitigate third-party risk — a fast-growing, business-critical capability for modern enterprises. As a Senior Software Engineer, you'll contribute as a core member of either the Vendor Lifecycle or Vendor Monitoring Experience team. You'll design and ship full-stack features that directly shape how customers manage vendor relationships, collaborate with product and design partners, and bring real engineering ownership to a product area that's growing quickly within Vanta. What you’ll do as a Senior Software Engineer at Vanta: Design, build, and maintain full-stack features across the TPRM product surface, including vendor onboarding, lifecycle management, and monitoring workflows Contribute to the vendor data model and core platform abstractions that power TPRM products Write clean, well-tested code and actively participate in code reviews; uphold engineering quality standards Engage in architecture discussions and contribute to technical decision-making within your team

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron's Global Supplier Quality organization is seeking a Controller Quality Principal Engineer to lead the quality strategy, qualification, and continuous improvement of storage and memory controller (ASIC/SoC) manufacturers supporting Micron's SSD, embedded, and storage solutions portfolio. This is a senior technical leadership role responsible for driving controller supplier quality performance from design qualification through mass production and field support The successful candidate will collaborate across functions with ASIC Development Team, Compose Engineering, Product Engineering, Dependability, Manufacturing, and Commodity Management, as well as directly with controller IC vendors, foundries, third party reliability labs and OSAT (outsourced assembly and test) partners, to ensure controller quality, reliability, and supply continuity meet Micron's standards. This role can be based in Taiwan, Hyderabad, or San Jose and will work extensively across time zones with global partners and suppliers! Develops, evaluates, revises, and applies technical quality assurance protocols/methods to inspect and test in-process raw materials, production equipment, and finished products. Ensures activities and items are in compliance with both company quality assurance standards and applicable government regulations. Performs analysis and identifies trends in the inspection of finished products, in-process materials and bulk raw materials, and recommends corrective actions when vital. Ensures that established manufacturing inspection, sampling and statisti

About the Team OpenAI's research training infrastructure powers how our frontier models are trained and evaluated. The Simulation team sits at the intersection between the agentic harness that powers OpenAI's products and the research infrastructure where GPT-next is trained, ensuring that our model's training environment is as realistic as possible. This team owns the integration layer that connects our production harness capabilities into the training stack. The work is highly cross-functional and high leverage: researchers depend on it to run experiments and evaluations reliably as well as to develop the next generation of harness capabilities. Failures in this surface can materially affect training velocity and correctness. About the Role We're looking for a Principal Software Engineer to lead the architecture and evolution of the Simulation Platform. You'll own a critical interface between research and engineering, building the systems, APIs, and operational patterns that let researchers use agentic coding infrastructure safely and effectively in training environments. This role is ideal for a senior backend or infrastructure engineer with strong technical judgment, product sense for highly technical users, and the ability to drive execution across multiple teams. The highest-leverage work is building robust infrastructure that supports and accelerates research without compromising engineering quality. In this role, you will Design, build, and evolve the integration between the Codex harness that powers OpenAI's products and research training infrastructure used for training GPT-next Build a platform for our LLMs to train and be evaluated in simulated environments that mimic their deployment setting as closely as possible, on every axis: agentic harness, compute substrate, timing, tools, data sources, humans in the loop, and more Own major integration surfaces end-to-end, from architecture and API design through rollout, operations, and long-term maintenance Bu

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a mid- to senior-level Physical Design Engineer who will contribute to the physical design of high-performance chips for industry-leading AI/ML architectures, spanning implementation from synthesis through tapeout. You will partner with front-end and physical design engineers to optimize floorplanning, timing, power, performance, and area across multiple IPs. Along the way, you will build end-to-end ASIC expertise while learning from experienced engineers across the chip development process. This role is hybrid , based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An engineer excited to work on high-performance designs for industry-leading AI/ML architectures. A collaborative problem solver who enjoys working with experienced engineers across ASIC disciplines. Grounded in logic design fundamentals and gate- and transistor-level implementation. Curious about how early architectural and RTL decisions shape physical implementation and final chip quality. What We Need A BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a relat

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an exceptional Senior-level Physical Design Engineer to drive top-level implementation of our complex AI and CPU System-on-Chip designs. You'll orchestrate cross-disciplinary collaboration, implementing sophisticated floorplans, power grids, and clock networks while ensuring design closure at the chip level. If you excel at managing the complexity of full-chip physical design and want to deliver next-generation AI hardware, we need your expertise. This role is hybrid , based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned physical design engineer who thrives on complex, full-chip implementation challenges. Expert at collaborating across disciplines, working effectively with architecture, RTL, and packaging teams. Passionate about optimizing chip-level implementations for power, performance, and area. Detail-oriented professional who drives design closure while maintaining quality and meeting aggressive schedules. What We Need 8+ years of top-level SOC physical design experience on complex, multi-million gate designs. Deep expertise in hierarchic

NVIDIA silicon runs the world's AI infrastructure. The frequency it delivers across every voltage, process corner, and workload is not assumed. It is measured, correlated, and validated. This role does that work. The Silicon Co-Design Group is where architecture intent becomes silicon reality. We own the boundary between what was designed and what was built, and we are the team that knows the difference. When a program ships at frequency and at quality, this team is a reason why. You will be the person who follows through between simulation and silicon. When the model is wrong, a frequency corner that doesn't hold, a Vmin that walks, a critical path that timing analysis missed, you find out why, and your data is what the rest of the program acts on. Architecture, design, and product teams do not guess. They use your numbers. The engineers who do this well are rare. They think like circuit designers, work like experimentalists, and reason like data scientists. If that is you, read on. What you'll be doing: Own silicon speed characterization from first power-on through production sign-off, covering frequency, Vmin, Vmax, and timing margins across the full PVT space. Close the correlation gap. Tie pre-silicon timing analysis and critical path predictions to measured silicon, quantify where the model diverges from reality, and produce analysis that architecture and design can act on with confidence. Trace failures to their source, whether a microarchitectural bottleneck, a critical path that doesn't close under voltage, a clocking issue, or a process corner the model didn't anticipate, and drive the resolution. Own and build AI agents that work at your direction: automated test orchestration, intelligent data pipelines, and analysis flows that expand coverage and compress cycle time without sacrificing difficulty. Know where AI accelerates real work and whe

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale. This is a senior, hands-on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure, physical design convergence, bring-up, and production readiness. You will plan and oversee the work of junior engineers and help drive and develop productive engineering relationships with external partners and help manage partner execution. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic as well as off-chip protocol bridges and interfaces. Drive third party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and de