Software Engineer Smart Contract Bridge in United States

Lead Design and Analysis Engineer (Electrical Systems Design) Company: The Boeing Company Boeing is currently hiring for a Lead Design and Analysis Engineer located in Berkeley, MO to be a part of the MQ-25 Electrical and Equipment Installation team. The MQ-25 Stingray is a new autonomous, unmanned carrier based refueling air vehicle. The selected candidate will be a part of aviation history by helping our Navy customer productization Autonomous Carrier landing, takeoff and refueling capabilities. The MQ-25 program is currently building the Engineering and Manufacturing Development (EMD) vehicles for the Navy. Additional work is under way for the beginning of the Low Rate Initial Production (LRIP) program for additional vehicles. The MQ-25 Electrical & Equipment team is responsible for the power architecture & design, electrical equipment technical management, electrical installation design, wire harness design, and integrating avionics and other equipment into the vehicle. This role will be focused on the power architecture & design. Position Responsibilities: Leads work with customers to develop and document complex electronic and electrical system requirements. Leads and coordinates work to analyze and translate requirements into system architecture, hardware and software designs and interface specifications. Leads work to test and validate to ensure system designs meet operational and functional requirements. Researches technology advances for potential application to company business needs. Makes recommendations for technology investments. This position is expected to be 100% onsite. The selected candidate will be require

Zscaler (NASDAQ: ZS) accelerates digital transformation so customers can be more agile, efficient, resilient, and secure. The Zscaler Zero Trust Exchange™️ platform protects thousands of customers from cyberattacks and data loss by securely connecting users, devices, and applications in any location. Distributed across 160+ public exchanges globally and thousands of private exchanges at the edge, the SASE-based Zero Trust Exchange is the world’s largest in-line cloud security platform. We believe the future of work is Human + AI and are building an AI-native enterprise where human potential is amplified by machine intelligence to solve the world’s hardest security challenges. Driven by deep customer obsession, we are committed to the mission, outcome, and to each other. We bring these commitments to life through three core behaviors: ownership and collaboration, trust through outcomes and impact, and a challenge culture with ongoing feedback. Ready to make an impact at the company pioneering security transformation in the AI era? Join us at Zscaler. Role We are looking for a Staff Site Reliability Engineer (Production Engineer) to join our team. This is a hybrid role (onsite three days a week in San Jose, CA or another Zscaler office; remote can be considered for exceptional candidates) reporting to the Senior Manager, Site Reliability Engineering in the Zero Trust Exchange department. As a key member of the Zero Trust Exchange team, you will own the systems-level reliability and performance of Zscaler’s high-throughput bare-metal and cloud infrastructure processing tens of billions of daily transactions across a global, multi-region fleet. This is a software-first SRE role: you will write production-grade code and automation, drive the shift from reactive incident response, and bring engineering discipline to the systems-level work - OS, network and application debugging - that keeps the fleet operating safely at scale. What You’ll Do (Role Expectations) Maintain h

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron-Boise, ID, we are undergoing a historic $15 billion investment in semiconductor manufacturing; construction began in early 2023, with DRAM production slated for the second half of the decade. As a leader in the semiconductor industry, we build solutions that encourage and transform technology. With plans to invest more than $150 billion globally over the next decade in groundbreaking manufacturing, we are looking for hardworking people to join our Boise expansion team and give to the growth and innovation of the semiconductor industry. ID1 High Volume Manufacturing Equipment Engineer is responsible for monitoring, sustaining, and improving the equipment while working in partnership with process team members and area engineers. In this position you will supervise tool performance, schedule and perform preventative maintenance on assigned tool sets, and use mechanical, electronic and PC/software skills to solve and repair equipment issues. They are also required to assist with equipment installations, engineering tests, build and modify equipment procedures, increase tool uptime through systematic problem solving and quality workmanship, and thoroughly document all maintenance. This is a hands-on equipment focused role with time spent in the fabrication facility. Responsibilities: Safely identify, handle, and work with chemicals and associated hazards in the work area. Recognize and respond appropriately to safety alarms and events, including EES, fire alarms, MDA, and ERT notifications. <l

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team to define and implement RTL for high-performance CPUs. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experienced in CPU microarchitecture with expertise in Rename, Scheduler, ROB, Load Store, Branch Prediction, Cache or Datapath. Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis. Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments. Background in microarchitecture definition, design specification, and performance-driven trade-off analysis. What We Need Own RTL design and microarchitecture development for a portion of a CPU block of a high-performance RISC-V CPU. Collaborate closely with DV, PD, and performance engineers to meet functional, timing, and power goals. Use innovative techniques to optimize power, performance, and

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Design Verification Engineer to lead pre-silicon verification of the Beowulf SoC, with focus on the Compute Subsystem (CSS), DDR memory subsystem, and Fabric NoC. This role will drive coverage, coherency, memory traffic, connectivity, error handling, and bring-up features critical to silicon success. This role is hybrid, based out of Boston, MA; Toronto, ON; or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Deeply curious about SoC architecture, compute systems, DDR behavior, and Fabric NoC/interconnect verification. Expert in UVM, SystemVerilog, coverage-driven verification, assertions, and subsystem-level debug. Experienced in verifying compute subsystems, DDR controllers and PHY-facing logic, NoC/interconnect protocols, coherency, ordering, and data movement. Comfortable with reset, power management, error handling, performance, and high-concurrency system scenarios. Proactive, detail-oriented, and effective in cross-functional technical discussions. Familiar with Python, C/C++, Tcl, CocoTB, or similar verification automation tools. What We Need Develop and own scalable verification environmen

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team to drive infrastructure for performance analysis, correlation and verification. You’ll work on a CPU based on RISC-V ISA, collaborating with core architects and RTL teams to deliver a highly efficient and performant design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Strong problem solver who can identify complex issues, develop practical solutions, and drive them through implementation. Enjoy building tools and improving the infrastructure, workflows, and methodologies that make CPU development more efficient. Skilled in C++ and Python, with experience using industry-standard compilation, simulation, and emulation tools. Experience with verification infrastructure and methodologies along with knowledge of high-performance CPU architecture and microarchitecture. Proficient in debugging RTL and logic across multiple design hierarchies and pre-silicon environments. What We Need Join a team driving improvements in CPU microarchitecture, verifying performance, and correlating results between RTL and the performance mode

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Design Verification Engineer to validate the System Management Controller (SMC) and enable seamless multi-chip integration. In this role, you will design and execute tests, build infrastructure, and debug issues across chiplet-based SoCs. You’ll have the opportunity to work with remote mentorship while contributing to the foundation of scalable multi-die systems. This role is hybrid, based out of Toronto, Ontario, Boston, MA or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Proficient in SystemVerilog, SV-UVM, Python, and C/C++ with strong verification skills. Experienced in writing test plans, building infrastructure, and debugging hardware/software flows. Comfortable working with remote mentorship and distributed teams. Familiar with AI-assisted tools like Copilot, Cursor, and Claude to accelerate verification. What We Need Develop and maintain SMC tests and supporting DV infrastructure. Write, execute, and track test plans for chiplet and multi-chip SoC designs. Use C/C++ to develop tests compiled, loaded, and executed directly on the DUT. Triage, analyze, and debug issues in clos

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a senior High Speed Interconnect / Signal Integrity Engineer to design and validate high-bandwidth links for large-scale AI systems. You will define, model, and qualify interconnect solutions across copper and optical technologies for next-generation AI inference and training clusters. This role is on-site in Santa Clara, CA, Austin, TX, or Toronto, Canada. We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting Who You Are An experienced electrical engineer with a Bachelor’s or Master’s in Electrical Engineering. 5+ years working on high-speed communications (100G–1.6T), including signal integrity, channels, and links. Comfortable building and owning link and channel budgets and making clear tradeoffs between reach, loss, BER, and margin. Hands-on with SI tools and lab equipment such as Keysight ADS, VNAs, TDRs, BERTs, and protocol analyzers. Familiar with cable specification and testing, as well as accelerated life testing, mating life, and failure analysis. Able to collaborate across hardware, systems, and manufacturing teams; manufacturing/DFM/DTM experience is a plus. What We Need Define and specify high-speed interconnect architectures

Principal Embedded SW/FW Engineer (Bringup) - Austin, Tx, USA Job Summary We have an exciting opportunity to be part of a collaborative, cross-functional development team validating cutting-edge, high-performance AI chips and platforms. You will play a key role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to provide technical guidance to other engineering team members. In this role, you can leverage our experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. The Team The Post-Silicon Bringup team sits within the Architecture and Validation team, we are responsible for bringup and validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and supporting the Silicon Characterisation team. Responsibilities and Duties Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon Deploy silicon validation tests on first silicon and debugging them Develop automated test framework and regression test suites in Python to optimize validation efficiency Collaborate closely with engineers from many other disciplines on a variety of topics Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies Analyse test results, identify and debug failures/defects Contribute to shared test and validation infrastructure Provide feedback to architects Candidate Profile Essential: Understanding of ML

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which the GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As a Developer Technology Engineer you will be at the forefront of innovation, working with leading industry partners and exciting OSS projects to accelerate RTX & DGX SoC performance for agentic use. This role offers an outstanding opportunity to collaborate with world-class talent and make a significant contribution to the next era of enterprise and consumer AI. What you'll be doing: Own key engagements with our fast-paced developer ecosystem partners, optimizing their applications to deliver outstanding end-to-end performance on RTX and DGX SoCs. Take ownership of performance optimization for compute-intensive CPU, AI, and 3D graphics workloads, working with domain experts to identify bottlenecks and implement effective solutions. Work across system software, GPU driver, architecture, and NVIDIA Research teams to influence next-generation, high-performance SoC platforms by bringing real-world workflows and actionable insights from partner and customer needs. Provide technical guidance and mentorship to junior engineers while contributing to an inclusive and high-performing team environment. What we need to see: BS or MS degree in Computer Science, Engineering, Mathematics or related degree (or equivalent experience) 5&#43; years of respective work experience as software developer Proficiency in C/C&#43;&#43;, Python, software

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Would you like to work in one of the most complex Fab environments in the world? As an industrial engineering intern in our research and development factory you will work on projects that further optimize our very automated factory. This role will provide exposure to larger data sets than you have ever worked with and will challenge your data management skills. Not only will this role significantly grow your skills but will also provide exceptional value to the organization on a real issue in our factory! Responsibilities: Identify key performance indicators for R&D program success. Use large data sources to extract and analyze planning data. Build reporting in Tableau and other systems to convey data to program teams. Construct infographics that display key information in easy-to-understand formats. Leveraging AI tools and find new ways to apply AI in the workplace. Minimum Qualifications: Working towards completion of a Bachelor’s or Master’s degree in the following areas: industrial engineering, manufacturing engineering, supply chain, Operations or other related discipline with expected graduation after this internship timeframe Must be a current student, and cannot graduate prior to September 2027. Ability to code in SQL, Python or similar to execute data extraction. Effective with Excel, Tableau or other data management and visualization software. Preferred Qualifications: Skille

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. NVIDIA has a rapidly expanding ecosystem of data center platform designs. From single node HGX/DGX systems all the way up to large multi-node NVLink domain rack architectures. These designs have become core to NVIDIA's rapidly growing enterprise and cloud provider businesses. Each brings together the full power of NVIDIA GPUs, NVIDIA NVLink, NVIDIA InfiniBand networking, NVIDIA Grace CPUs, and a fully optimized NVIDIA AI and HPC software stack. We are searching for a highly motivated engineer to lead performance benchmarking and optimization efforts for our data center products. You will be instrumental in ensuring our data center solutions deliver industry-leading performance for accelerated computing workloads. What you will be doing: Design and execute comprehensive performance benchmarking strategies for our data center platforms and products Characterize real-world AI training, inference, and HPC workloads at scale Define, track, and report key performance indicators (throughput, latency, efficiency, scaling) Build automation tools and frameworks for performance monitoring and analysis Identify and analyze performance bottlenecks across compute, memory, network and storage subsystems Work closely with architecture, hardware,

As a Forward Deployed Engineer on the Feature Flags team, you'll partner directly with customers to accelerate their feature flag implementations — from initial architecture consulting through prototype builds to full-scale migrations. This role is for someone who wants to write code with customers, not just advise them. You'll work hands-on inside customer codebases to unblock complex, high-stakes deployments, directly influencing deal velocity and customer success. Working closely with Sales, Solutions, and Engineering, you'll be the technical force that turns a signed contract into a live, adopted implementation. What You'll Do: Serve as the hands-on technical partner for strategic customers implementing Datadog Feature Flags, from pre-sales technical validation through post-sales delivery Consult on flag architecture and implementation approach for complex environments — multi-service, multi-platform, high-scale deployments Build prototype flag implementations directly in customer codebases to prove value and de-risk technical decisions early in the sales cycle Implement flags across diverse and advanced deployment modes (server-side, client-side, edge, mobile, streaming/real-time) tailored to each customer's stack Drive full flag migrations to completion — including legacy system cutover — efficiently and with minimal customer engineering burden Identify patterns across customer implementations and feed them back to Product and Engineering to improve the core product and reduce future implementation time Collaborate closely with Engineering on technical edge cases, product gaps, and implementation tooling Partner with Sales and Solutions to accelerate deal cycles by removing technical risk and uncertainty Who You Are: 5 years of professional software engineering experience, with hands-on coding ability across the stack you're deployed into Experience with feature flagging, experimentation, or config management systems (internal or vendor) Comfortable dropping i

ABOUT BASETEN Baseten powers mission-critical inference for the world's most dynamic AI companies, like Cursor, Notion, OpenEvidence, Abridge, Clay, Gamma and Writer. By uniting applied AI research, flexible infrastructure, and seamless developer tooling, we enable companies operating at the frontier of AI to bring cutting-edge models into production. We're growing quickly and recently raised our $1.5B Series F , led by Altimeter Capital, Conviction Partners, and Spark Capital. Join us and help build the platform engineers turn to to ship AI products. THE ROLE We are looking for an IT Support / Operations Engineer to join Baseten as we continue to scale our IT team. In this role, you will play a critical part in bringing our technical support entirely in-house to provide a seamless, high-touch experience for all Baseten employees. As we continue to scale, you will be the primary point of contact for day-to-day technical issues, allowing you to have a direct impact on our team's productivity and overall office environment. This position is ideal for a hands-on problem solver who enjoys a mix of hardware and software troubleshooting, user lifecycle management, and maintaining the physical IT infrastructure of a modern office. While you will focus heavily on elevating our internal support standards, you will also assist with systems administration and workflow automation as our company evolves. This is a hybrid role based out of our San Francisco or New York office, following our standard policy of three days per week in-person to ensure our physical office and AV systems remain high-performing and reliable. RESPONSIBILITIES Serve as the escalation point for day-to-day technical support, diagnosing and resolving hardware and software issues across our Mac and Windows fleet Manage user lifecycle administration including provisioning, deprovisioning, and access management across all systems and services Own the IT onboarding experience for new employees — from laptop set

The Team We are Datadog’s in-house product experts. The Technical Solutions team enables Datadog’s worldwide growth by educating potential partners and ensuring that our integration ecosystem is high-performing, secure, and valuable. Partner Technology Solutions Engineers (TSEs) are the technical bridge between Datadog and our third-party developer community. We act as consultants, helping partners build world-class monitoring solutions on the Integration Developer Platform (IDP) . The Opportunity Datadog is looking for a Partner Technology Solutions Engineer to join our fast-paced team. You will be the primary technical contact for our partners, guiding them through the entire integration lifecycle—from initial architectural design to final publication on the Datadog Marketplace. This is a unique role that combines deep technical troubleshooting with high-level consulting and platform advocacy. You will work directly with external developers and see your contributions immediately reflected in the Datadog ecosystem. You Will Act as the technical lead for partners, advising on OAuth flows, log pipelines, OpenTelemetry, and agent-based vs. API-based configurations Perform architectural assessments and deep-dive code reviews for partner integrations in the integrations-extras and marketplace repositories, ensuring they meet our Quality Rubric Solve complex technical challenges for partners via Zendesk, Slack, and dedicated technical consultations Identify friction points in our Integration Developer Platform (IDP) and partner with our internal Product and Engineering teams to build a better developer experience Maintain public-facing developer documentation and internal tracking systems ( JIRA ) to ensure transparency and scale You Are A technical expert with 3+ years of experience in a technical role (Support Engineering, Solutions Architecture, or Software Development) Proficient in at least one language (Python or Go preferred) An observability enthusiast who unders