System Engineer in United States

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale. This is a senior, hands-on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure, physical design convergence, bring-up, and production readiness. You will plan and oversee the work of junior engineers and help drive and develop productive engineering relationships with external partners and help manage partner execution. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic as well as off-chip protocol bridges and interfaces. Drive third party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and de

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We're seeking a Security Engineer to join our First-Party Hardware team. In this role, you will own the end-to-end security foundation for OpenAI's first-party AI hardware systems, working across hardware security, embedded security, system security, and practical deployment at data center scale. You will partner with silicon, hardware, firmware, infrastructure, manufacturing, operations, and security teams to define and deliver system-level device trust. This includes boot integrity, device identity, provisioning, attestation, management-plane security, storage encryption, debug controls, firmware update and recovery, RMA, and decommissioning. You will be accountable for turning threat models into requirements, requirements into implementation, and implementation into validation evidence that can support launch decisions. Location: San Francisco, CA (Hybrid: 3 days/week onsite) Relocation assistance available. In this role, you will: Own security requirements, threat models, validation strategy, and launch-readiness evidence for first-party hardware platforms from early design through production deployment. Design and review secure boot, measured boot, roots of trust, platform firmware resilience, firmware signing, recovery, and anti-rollback strategies across heterogeneous devices. Own device identity, provisioning, enrollment, attestation, certificate lifecycle, and key-management requirements across manufacturing and data center bring-up. Harden management

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role You will develop and evolve the tooling ecosystem that hardware engineers rely on every day — from hardware compilers and IR transformations to simulation, debugging, and automation infrastructure. The work spans software engineering, compiler concepts, and practical hardware workflows, with direct impact on how quickly and effectively we design next-generation AI systems. You’ll collaborate closely with architects, RTL designers, and verification engineers to translate real engineering friction into durable, scalable tooling solutions. In this role you will: Build and improve the software tooling that makes hardware teams faster: compilation, IR transforms, RTL generation, simulation, debug, and automation. Extend and integrate hardware compiler stacks (frontends, IR passes, lowering, scheduling, codegen to Verilog/SystemVerilog) and connect them to real design workflows. Improve developer experience and reliability: reproducible builds, better error messages, faster iteration loops, and dependable CI and regression infrastructure. Work closely with designers and verification engineers to turn real pain points into durable tools. Dive into RTL when needed: read and reason about Verilog/SystemVerilog to debug issues, validate tool output, and improve debuggability. Be willing to go all the way down the stack when necessary, including gate-level views, synthesis results, and implementation artifacts. Help enable PPA optimization loops by building analysis and au

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for an embedded engineer to help build firmware and associated modeling software for OpenAI’s in house AI accelerator. This role involves designing and developing drivers and functional models for a large array of HW components, writing high throughput and low latency firmware code, investigating bring-up and production issues. Responsibilities Design and implement drivers for hardware peripherals, including those related to AI chips. Design and implement functional software models to simulate SoC uncore logic and enable FW testing against the model Design and implement low-latency and high throughput embedded SW to manage HW resources. Work with adjacent software and hardware teams to implement requirements, debug issues and shape future generations of the hardware. Collaborate with vendors to integrate their technologies within our systems. Bring up and debug firmware/driver on new platforms. Come up with processes and debug issues raised in the field. Set up monitoring, integration testing and diagnostics tools. Qualifications 5+ years of experience working in embedded SW space. Ability to thrive in ambiguity and learn new technologies. Strong programming skills in C/C++ and/or Rust. Experience developing high throughput, low latency and multi-threaded code. Experience working with real time operating systems (RTOS). Experience developing hardware drivers and working with hardware Experience with HW/SW co-design Knowledge of common embedded pr

About the Team: OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale. In this role you will: Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality. Define verification plans based on architecture and microarchitecture specs. Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies. Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness. Drive bug triage, root cause analysis, and work closely with design teams on resolution. Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments. You might thrive in this role if you have: BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification. Proven success verifying complex IP or SoC designs in industry-standard flows Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi). Strong knowledge

About the team: OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the role: We are seeking an experienced Optical Network Engineer to lead Laser related work within our optical interconnect efforts for large-scale compute systems. The role also requires broad, hands-on optical validation experience across IM/DD-based interconnects, working from lab characterization through production readiness and scaled deployment. In this role you will: Drive laser-focused requirements and technical direction within the broader optical interconnect roadmap. Lead evaluation and validation of optical components and subsystems, including laser-based elements, in lab and production-representative environments. Support end-to-end optical testing for IM/DD interconnects (e.g., module/system bring-up, characterization, debug, and readiness for scale). Work with external partners to align on development milestones, performance targets, and quality expectations. Own technical issue triage and resolution across performance, reliability, and manufacturability topics. Collaborate across internal teams to support integration, rollout, and operational success at scale. You might thrive in this role if you have: Strong experience in laser-focused optical engineering (development, validation, manufacturing readiness, or field support). Broad hands-on background with IM/DD optical technologies and optical test/debug workflows. Experience working with external suppliers/manufacturing partners and production-oriented execution. Demonstrated ability to debug complex t

Work Flexibility: Hybrid or Onsite Join Stryker’s Global Robotics Customer Care team and support the engineering processes that help maintain and improve service operations for the Mako robotic system and related technologies. This role offers the opportunity to contribute to process development, product lifecycle activities, and continuous improvement initiatives within a regulated medical technology environment. The Process Engineer will support repair, upgrade, and service processes while collaborating across functions to ensure quality, compliance, and operational efficiency. What You Will Do Support new product and process introductions by executing engineering activities and maintaining required documentation in accordance with established development procedures. Lead process and procedure updates related to product launches, product integrations, process improvements, and audit readiness activities. Identify and implement continuous improvement initiatives that enhance service operations, process efficiency, quality, and customer experience metrics. Conduct process investigations, experimental testing, equipment analysis, and validation activities to support repair and upgrade operations. Train service personnel on new processes and procedures while ensuring compliance with quality, safety, and regulated industry requirements. What You Will Need Required: Bachelor’s degree in Engineering or a related technical field. Minimum 0 years of relevant engineering experience. Ability to read and interpret engineering drawings. Working knowledge of geometrical dimensioning and tolerancing (GD&T). Preferred: Minimum 1 year of experience in process engineering, manufacturing engineering, service engineering, or a related field.</

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for a product manufacturing & quality engineer, who will be responsible for driving technical initiatives related to the manufacturing, quality and reliability of our AI supercomputer hardware systems to ensure product success from concept to launch and through mass production. You’ll have the opportunity to coordinate with functional SMEs and work with a wide range of stakeholders, from design engineering and operations teams, TPMs, external industry vendors and partners to ensure that all products are developed and delivered on time and to the highest quality standards. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees In this role, you will: Own the integrated manufacturing and quality readiness for a product across L6, L10, and L11, with clear gates, milestones, deliverables, owners, and closure criteria. Lead readiness of process flows, tooling, fixtures, assembly operations, test interfaces, and production controls. Review and contribute to work instructions. Translate product requirements into qualification plans, process controls, test requirements and acceptance criteria with design engineering and Area SMEs Coordinate and drive execution of product and process qualification, reliability testing, and validation with the relevant SMEs. Maintain traceable evidence that assigned products and processes meet agreed performance, reliability,

We are the GPU Communications Libraries and Networking team at NVIDIA. We deliver communication libraries like NCCL, NVSHMEM, UCX for Deep Learning and HPC. DL and HPC applications have a huge compute demand already and run on scales which go up to tens of thousands of GPUs. The GPUs are connected with high-speed interconnects (eg. NVLink, PCIe) within a node and with high-speed networking (eg. Infiniband, Ethernet) across the nodes. Communication performance between the GPUs has a direct impact on the end-to-end application performance; and the stakes are even higher at huge scales! We are looking for a technical leader to manage our NVSHMEM and UCX libraries. This is an outstanding opportunity to push the limits on the state-of-the-art and deliver platforms the world has never seen before. Are you ready for to contribute to the development of innovative technologies and help realize NVIDIA's vision? What you will be doing: Lead, mentor, and grow your library engineering team and be responsible for the planning and execution of projects as well as the quality, and performance of your libraries. This is a technical leadership role so you will participate in feature design and implementation. Interact with internal and external partners and researchers to understand their use cases and requirements. Collaborate with engineering teams, program and product management, and partners to define the product roadmap. Continuously review and identify improvement opportunities in established processes, infrastructure, and practices to ensure the teams are executing in the most efficient and transparent manner. What we need to see: 10&#43; overall years of experience in the software industry with specialization in HPC networking or system software. 4&#43; years of management experience. BS, MS, or Ph.D. in C

NVIDIA is seeking a Senior Firmware Engineer to join our CSP Engagements team, focusing on system software for Datacenter products such as GB200. This role combines deep technical expertise in embedded firmware development with customer-facing responsibilities to enable cloud service providers with next-generation computing platforms. You will work at the intersection of hardware and software, driving technical solutions from concept through deployment. What you will be doing: Design and develop firmware solutions for manageability and observability of data center servers. Actively participate in hardware bring-up activities, OOB firmware development, protocol stacks (Redfish, PLDM, MCTP, NSM) and hardware-software co-design for Cloud Service Provider deployments. Debug and troubleshoot NVIDIA GPU firmware issues, power management, performance, and thermal control problems for data center deployments, providing active support to CSPs. Partner directly with CSPs to deliver technical solutions, co-develop & co-debug features and optimizations, and provide support during new product introductions. Perform advanced system debugging, root cause analysis, and performance optimization for large-scale data center environments. Collaborate with AE, FAE, and Solution Architect teams to deliver integrated customer solutions and technical documentation. What we need to see: Deep expertise in data center server architectures, HPC systems, and hardware-software co-design. Deep expertise in embedded firmware, server management controllers, and hardware bring-up with proven track record of shipping production BMC solutions Strong knowledge of DMTF protocols (Redfish, IPMI, PLDM, MCTP, SPDM), telemetry frameworks, and out-of-band management architectures Expert-level skills in C/C&

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. Role Overview We are seeking an experienced ASIC Package Signal Integrity / Power Integrity Engineer to drive electrical architecture, modeling, optimization, and validation for the most advanced AI/HPC silicon and package design. This role focuses on high-speed SerDes and memory channel architecture, advanced 2.5D/3D package SI/PI, substrate to package co-design, power-delivery-network optimization, electromagnetic modeling, and simulation-to-measurement correlation. The ideal candidate has strong hands-on experience with high-speed channel and PDN analysis across ASIC packages, interposers, substrates, and power-delivery structures, and can translate simulation results into practical design requirements for interposers and package substrate design optimization. The engineer will work closely with ASIC, package, system, mechanical, thermal, power, and silicon validation teams from early architecture and feasibility studies through production bring-up. In this role you will Own SI/PI architecture and analysis for advanced AI ASIC packages from early feasibility studies through production. Develop and optimize high-speed electrical channels for 200G/400G SerDes, PCIe, HBM, DDR, and chiplet/die-to-die interfaces. Perform package, interposer and substrate modeling using 2D/3D electromagnetic solvers. Define and optimize package stack-ups, transmission-line structures, via transitions, breakout structures, return paths, ground shielding, bump maps, and ball maps based on SI/PI re

At Linear, we're building the product development system for teams and agents. AI is fundamentally changing how software gets built, and we’re shaping the tools this new era requires. Founded in 2019, Linear has become the platform of choice for more than 40,000 companies (including OpenAI, Coinbase, and Ramp) to plan, build, and ship their products. Today, our team is distributed across North America, Europe, and Australia, and we’re continuing to grow internationally. What unites us is relentless focus, fast execution, and a deep care for software craftsmanship. As a small team, we’re all generalists that work across the full stack (built in Typescript end-to-end). We’re looking for experienced engineers that thrive in an environment of autonomy and individual responsibility to help us build the future of product development. Location & work mode Linear is a remote-first company, with optional co-working offices in San Francisco, New York, and London. This role is open to candidates based in the US and Europe. You can work from anywhere within these regions. We value deep focus and async collaboration, with intentional moments to connect in person through team off-sites, optional co-working, and occasional travel. What you'll do Work closely with founders and design to implement new concepts and ideas Build AI-powered functionality into the core of Linear Update our realtime collaborative content editor used across all internal surfaces Build new user-facing features with beautiful and scalable UI components Obsessively improve application performance Refine our software development processes to keep the team operating at high velocity What we're looking for 5+ years of experience building customer-facing products at a high-quality software company Strong React and TypeScript fundamentals, with experience across the full stack (Browser technologies, Node, GraphQL, PostgreSQL) Track record of driving complex, end-to-end features (not just incremental improvemen

At Linear, we're building the product development system for teams and agents. AI is fundamentally changing how software gets built, and we’re shaping the tools this new era requires. Founded in 2019, Linear has become the platform of choice for more than 40,000 companies (including OpenAI, Coinbase, and Ramp) to plan, build, and ship their products. Today, our team is distributed across North America, Europe, and Australia, and we’re continuing to grow internationally. What unites us is relentless focus, fast execution, and a deep care for software craftsmanship. As a small team, we’re all generalists that work across the full stack (built in Typescript end-to-end). We’re looking for experienced engineers that thrive in an environment of autonomy and individual responsibility to help us build the future of product development. Location & work mode Linear is a remote-first company, with optional co-working offices in San Francisco, New York, and London. This role is open to candidates based in the US and Europe. You can work from anywhere within those regions. We value deep focus and async collaboration, with intentional moments to connect in person through team off-sites, optional co-working, and occasional travel. What you'll do Build new user-facing features with everything from database models to GraphQL resolvers and UI components Optimize our data synchronization stack by applying better serialization protocols Add real-time collaborative editing to our content editor Improve performance by profiling and tweaking virtualized list rendering Add analytics, monitoring, and alerts to our service so that we can better respond to operational incidents Open-source any non-trivial innovations that come out of our work on the product Redefine best-in-class software development processes so that we can build a purpose-built product. What we're looking for 5+ years of experience building customer-facing products at a high-quality software company Strong React and Typ

At Linear, we're building the product development system for teams and agents. AI is fundamentally changing how software gets built, and we’re shaping the tools this new era requires. Founded in 2019, Linear has become the platform of choice for more than 40,000 companies (including OpenAI, Coinbase, and Ramp) to plan, build, and ship their products. Today, our team is distributed across North America, Europe, and Australia, and we’re continuing to grow internationally. What unites us is relentless focus, fast execution, and a deep care for software craftsmanship. We’re looking for experienced engineers who have shipped applied AI systems to production and want to define what the agent-native future looks like. We are building intelligence into the core of Linear, enabling the product to orchestrate coding, proactively move work forward, and power-up every software team. You’ll work closely with product and design to transform foundation models into structured, reliable workflows embedded deeply in the core of Linear. We care deeply about keeping Linear fast, intuitive, and opinionated—AI is no exception. Location & work mode Linear is a remote-first company, with optional co-working offices in San Francisco, New York, and London. This role is open to candidates based in the North America. You can work from anywhere within this region. We value deep focus and async collaboration, with intentional moments to connect in person through team off-sites, optional co-working, and occasional travel. What you'll do Build AI-powered product features that feel native, fast, and delightful to use Work with product and design to prototype and iterate on intelligent workflows and user interactions Design backend services to power natural language interfaces, smart suggestions, agentic workloads, and more Optimize prompts, fine-tune model behavior, and evaluate performance Help to guide our agent platform, allowing third parties to bring agents into the core Linear experience

What you’ll do Act as the technical lead for large parts of the scanner platform: system architecture, codebase structure, and long-term maintainability. Own core runtime foundations: distributed control, state management, fault handling, and reliability. Drive engineering rigor: testability, code quality, review standards, performance regression prevention, and release processes. Build robust observability: logs, metrics, traces, and replayable diagnostics (with privacy constraints). Collaborate with hardware and recon/ML teams to define interfaces, data contracts, timing/synchronization, and failure modes. Lead complex refactors (e.g., message passing / RPC boundaries, modularization, concurrency model) without halting forward progress. What we’re looking for Deep software architecture experience for real-world systems: robotics, instrumentation, medical devices, or other complex distributed products. Strong Python and concurrency background (asyncio, multiprocessing, profiling, performance engineering). Track record of shipping systems that are observable, debuggable, and resilient. Strong technical leadership: clarity, pragmatic trade-offs, and mentoring. Useful experience Building but rock-solid systems: clear interfaces (gRPC/protobuf or equivalent), strong state modeling, and failure handling. High-leverage engineering habits on a lean team: good tests, CI, reproducible dev environments, and fast code review. Practical performance + concurrency work in Python (asyncio, profiling, multiprocessing) and comfort debugging distributed behavior. Security-minded device software: safe defaults, encrypted data paths, and disciplined handling of PII/PHI. Operational thinking: remote updates/management, excellent logging, and diagnostics that make real hardware debuggable.