Hardware Platform Security Architect in India

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We’re looking for a hands-on RTL Design Engineer to own the microarchitecture and RTL implementation of the Power Management Subsystem/Interrupt Controllers/AXI Interconnect/Cache Controller . You’ll collaborate with cross-functional teams—architecture, firmware, software, DV, and PD—to define, design, and optimize power management solutions for next-generation RISC-V/ARM-based SoCs. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels. During the interview process, you will beevaluated and offered a level that aligns with your experience, which may differ from the one in this posting. Who You Are 5–10 years of experience in ASIC/SOC/IP design, with hands-on experience in microarchitecture and RTL development Skilled in Verilog/SystemVerilog and comfortable working across design, debug, and analysis Design and develop microarchitectures for a set of highly configurable IPs Microarchitecture and RTL coding ensuring optimal performance, power, area Work with verification teams on assertions, test plans, debug, coverage, etc. Deep understanding of power management concepts—clocking, reset, DVFS, and low-power modes Familiar with RISC-V or ARM-based SoCs and standard bus protocols (AXI, AHB, APB, CHI) Awareness of functional safety (ISO 26262) practices in hardware design What We Need Abil

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is building the future of AI compute, and this role will build the talent pipeline that makes it possible. As an Early Talent Recruiter, you will own university and early-career recruiting for your site, shaping which schools we invest in, building relationships with students and faculty, and leading intern, co-op, and new-grad hiring from first outreach through accepted offer. You will not simply run an existing campus calendar. You will decide where to focus, raise the quality of the funnel, and build the recruiting motion that our growing hardware and software teams need. This role is hybrid, based out of Tokyo, Japan, Bangalore, India, or New Taipei City, Taiwan. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You have owned a full campus recruiting cycle, including school selection, university partnerships, sourcing, screening, interview coordination, offer management, and closing. You use judgment and influence to partner with hiring managers, challenge assumptions when needed, and hold a clear hiring bar without relying on authority. You work from funnel data and can connect measures such as applications, conversions

Job Summary Reporting to the Memory Validation leadership team, the Senior Silicon DDR/HBM Validation Engineer will be responsible for the bring-up, validation, characterization and debug of advanced memory subsystems used in next-generation AI compute platforms. The role will focus on DDR and HBM technologies, working closely with silicon design, firmware, characterization, platform and systems teams to ensure robust memory subsystem functionality, performance and reliability. The successful candidate will take ownership of significant validation activities, contribute to debug and root-cause analysis efforts, and help improve validation methodologies, automation and infrastructure. The Team The Memory Validation team sits within the Validation organisation and is responsible for the bring-up, validation, characterization and debug of memory subsystems across Graphcore silicon and platform products. The team supports DDR and HBM validation activities throughout the product lifecycle, from first silicon through production readiness. Engineers work closely with architecture, RTL, firmware, characterization, systems and platform teams to ensure memory technologies meet functionality, performance, reliability and performance objectives. Responsibilities and Duties Execute validation and bring-up activities for DDR and HBM memory subsystems Verify memory bring-up software, firmware and scripts against defined project requirements Debug firmware, hardware and system-level issues and contribute to root-cause analysis activities Analyse system logs, validation data and characterization results to identify failures and performance issues Perform PHY characterization and analog-level analysis during stress testing and validation activities Develop and execute functional, stress, performance and corner-case validation tests Perform signal integrity, voltage, frequency and timing measurements using laboratory instrumentation Char

🚀 About WRITER WRITER is where the world's leading enterprises orchestrate AI-powered work. Our vision is to expand human capacity through superintelligence. And we're proving it's possible – through powerful, trustworthy AI that unites IT and business teams together to unlock enterprise-wide transformation. With WRITER's end-to-end platform, hundreds of companies like Mars, Marriott, Uber, and Vanguard are building and deploying AI agents that are grounded in their company's data and fueled by WRITER's enterprise-grade LLMs. Valued at $1.9B and backed by industry-leading investors including Premji Invest, Radical Ventures, and ICONIQ Growth, WRITER is rapidly cementing its position as the leader in enterprise generative AI. Founded in 2020 with office hubs in San Francisco, New York City, Austin, Chicago, and London, our team thinks big and moves fast, and we're looking for smart, hardworking builders and scalers to join us on our journey to create a better future of work with AI. 📐 About the role As a Corporate it engineer at WRITER, you'll be the backbone of our internal technology ecosystem. You'll design, build, and scale the systems that empower our rapidly growing team to do their best work. This isn't just about closing tickets; it's about architecting seamless, secure, and automated experiences across our entire SaaS and hardware landscape. You'll have the opportunity to shape how a leading AI company operates from the inside out, ensuring our infrastructure scales as fast as our ambitions. This role is hybrid and based out of our San Francisco or New York City office hubs. You will report to Staff IT lead 🦸🏻‍♀️ What you'll do Own the architecture and administration of our core enterprise SaaS platforms — including Google Workspace, Slack, and Okta Build robust automations and API integrations using Python and Terraform to eliminate manual IT processes and engineer zero-touch onboarding and offboarding for our global workforce Drive our identity and acc

🚀 About WRITER WRITER is where the world's leading enterprises orchestrate AI-powered work. Our vision is to expand human capacity through superintelligence. And we're proving it's possible – through powerful, trustworthy AI that unites IT and business teams together to unlock enterprise-wide transformation. With WRITER's end-to-end platform, hundreds of companies like Mars, Marriott, Uber, and Vanguard are building and deploying AI agents that are grounded in their company's data and fueled by WRITER's enterprise-grade LLMs. Valued at $1.9B and backed by industry-leading investors including Premji Invest, Radical Ventures, and ICONIQ Growth, WRITER is rapidly cementing its position as the leader in enterprise generative AI. Founded in 2020 with office hubs in San Francisco, New York City, Austin, Chicago, and London, our team thinks big and moves fast, and we're looking for smart, hardworking builders and scalers to join us on our journey to create a better future of work with AI. 📐 About the role As a Corporate it engineer at WRITER, you'll be the backbone of our internal technology ecosystem. You'll design, build, and scale the systems that empower our rapidly growing team to do their best work. This isn't just about closing tickets; it's about architecting seamless, secure, and automated experiences across our entire SaaS and hardware landscape. You'll have the opportunity to shape how a leading AI company operates from the inside out, ensuring our infrastructure scales as fast as our ambitions. This role is hybrid and based out of our London office hub. You will report to Staff IT lead 🦸🏻‍♀️ What you'll do Own the architecture and administration of our core enterprise SaaS platforms — including Google Workspace, Slack, and Okta Build robust automations and API integrations using Python and Terraform to eliminate manual IT processes and engineer zero-touch onboarding and offboarding for our global workforce Drive our identity and access management strategy b

About the Role At Together AI, you’ll build and operate one of the world’s largest GPU fleets used for frontier model training and inference. This isn’t a traditional infrastructure role—we’re looking for engineers who love building systems, automating everything, and solving problems at massive scale. If you enjoy writing software more than clicking dashboards, obsess over eliminating manual work, and want to build infrastructure that manages tens of thousands of GPUs autonomously, we’d love to talk. Responsibilities Design and build fleet automation systems that provision, validate, deploy, upgrade, repair, and retire GPU clusters with minimal human intervention. Build AI Infrastructure Agents that automate deployment, root-cause failures, incident triage, and autonomous remediation. Develop Fleet Intelligence platforms that continuously monitor hardware health, firmware, networking, storage, thermals, and workload performance to predict failures before they impact customers. Build software that maximizes GPU availability, utilization, performance, and reliability across thousands of accelerators. Create automated validation systems for GPUs, InfiniBand/RoCE fabrics, NVLink/NVSwitch, storage, and distributed AI workloads. Build internal platforms and developer tools that allow infrastructure to be managed through software—not manual operations. Continuously improve deployment velocity, reliability, and operational efficiency through automation. Partner closely with hardware, networking, platform, and AI teams to push the limits of AI infrastructure. Requirements 3+ years building distributed systems, infrastructure platforms, or large-scale backend software. Strong software engineering skills in Python, Go, or Rust . Experience building platforms, automation systems, or developer infrastructure. Experience with Linux, Kubernetes, Terraform, Ansible, or similar infrastructure technologies. Strong systems thinking with the ability to understand problems across hardw

Role: Network Engineer Location: Gurgaon Graviton is a privately funded quantitative trading firm striving for excellence in financial markets' research. We are seeking a Network Engineer for our team in Gurgaon. Graviton trades across a multitude of asset classes and trading venues using a gamut of concepts and techniques ranging from time series analysis, filtering, classification, stochastic models, pattern recognition to statistical inference analysing terabytes of data to come up with ideas to identify pricing anomalies in financial markets. Key Responsibilities Design, deploy, operate, and troubleshoot low-latency network infrastructure used by trading firms. Manage connectivity to global stock exchanges, brokers, market-data providers, and ISPs. Build and maintain colocation infrastructure including routers, switches, Layer-1 devices (added advantage), structured cabling and cross connects. Configure and support Cisco Nexus, Arista and similar platform devices. Design and troubleshoot Layer 2 and Layer 3 networks including: VLANs, VRFs, BGP, OSPF, Static routing, PIM, IGMP, Multicast, SSM, ACLs and QoS. Troubleshoot packet loss, multicast issues, duplicate packets, IGMP/PIM and multicast/BGP routing. Monitor and optimize latency, jitter, packet loss, interface errors, congestion, and network performance. Work with ultra-low-latency technologies including: Cut-through switching, Layer-1 switches, FPGA-based network devices, Kernel-bypass networking, ExaNIC/Solarflare NICs, Hardware timestamping. Configure and troubleshoot PTP and clock synchronization infrastructure. Perform server and network equipment installation in exchange and third-party data centres. Manage rack layout, patching, cable optimization, optics, DACs, cross-connects, and inventory. Coordinate network changes with exchanges, telecom providers, brokers, vendors, and data-centre teams. Plan and execute production changes during approved maintenance windows. Perform pre-change validation, c

Job Details: Job Description: Intel India Customer Engineering Team is in a mission to create successful Original Design Manufacturers (ODMs) from India across their customer base. We are seeking a Hardware Board Design Engineer specializing in Power Delivery design and debug experience to help Intel customers design and debug their hardware platforms based on Intel Core and Atom CPUs. Qualifications: • Education : Bachelor's or Master's degree in Electronics/Electrical Engineering or related field • Experience : 7-12 years of industry experience (preferably 5-6 years designing and debugging hardware boards with Power Delivery focus using Intel Core/Atom CPUs) • Power Delivery Expertise : Deep understanding of system Power Delivery requirements and familiarity with Intel Core/Atom processor Power Delivery guidelines including IMVP specifications and PDN analysis • Circuit Design : Extensive experience with Buck, Boost, and Multi-phase Power Delivery Network design, including control loop understanding and very high current/low-voltage power delivery design • Design Tools : Proficiency in schematic capture using ind

NVIDIA has been redefining computer graphics, PC gaming, and accelerated computing for more than 25 years. Today, we are tapping into the unlimited potential of AI to define the next era of computing. As an NVIDIAN, you will address challenges spanning architecture, silicon, firmware, software, and production — and excellent judgment matters as much as technical depth! Every major NVIDIA silicon product family—from the chips powering AI and datacentre systems to gaming, professional, embedded, and automotive platforms—passes through our productization work on its way to production. NVIDIA’s Silicon Co-Design Productization team works from pre-silicon strategy and feature development through bring-up, characterization, correlation, and optimization. Our charter spans power & performance modelling, bring up & tuning of low-power features, power & thermal controllers , and system-level optimization that ultimately shape how NVIDIA products are configured, binned, specified, and shipped. What you'll be doing Drive silicon power productization from pre-silicon planning through bring-up and production, including test strategy, feature readiness, characterization, and optimization. Partner with architecture and design teams to identify improvements, validate features, and help translate them into production-ready solutions. Correlate measured silicon behaviour with pre-silicon expectations, investigate gaps, and drive complex issues to root cause. Build power and performance models and characterization methodologies that decide silicon binning, product specifications, productization decisions, and customer guidance. Use AI/ML and data-driven methods to analyse characterization & telemetry data, identify anomalies & trends , and accelerate issue debug across silicon, board, power delivery, firmware,

IoT Hardware Engineer Build the Future of Smart Connected Devices Join our growing team as an IoT Hardware Engineer and work on exciting IoT solutions that combine electronics, embedded systems, and smart technologies. We are looking for a passionate, hands-on engineer who enjoys designing, building, testing, and improving real-world connected devices. Key Responsibilities: Design, develop, and prototype IoT devices using ESP32 microcontrollers. Develop and integrate firmware, hardware components, and embedded systems. Select and evaluate sensors, actuators, communication modules, and electronic components for IoT applications. Participate in hardware design reviews and product improvement discussions. Assemble, test, and debug electronic prototypes for performance and reliability. Troubleshoot hardware and software issues using professional debugging techniques. Required Skills & Experience: ITI, Diploma in IT Hardware Engineering, Computer Engineering, Electronics, or related field (highly preferred). Strong experience in programming and working with microcontrollers, especially ESP32. Experience with embedded platforms such as ESP32, STM, and similar systems. Knowledge of sensor interfacing using I2C, SPI, UART, and other communication protocols. Excellent PCB soldering skills and experience building complex electronic prototypes. Strong understanding of electronics fundamentals including resistors, voltage levels, power management, and circuit design. Ability to use testing tools such as oscilloscopes and logic analyzers for debugging circuits. Preferred Skills: Experience with KiCad or other hardware design tools. Knowledge of low-power design techniques for battery-operated IoT devices. Understanding of power optimization and embedded system efficiency. Familiarity with Agile development methodologies. Who We’re Looking For: A creative and skilled IoT enthusiast who loves turning ideas into working hardware products. If you enjoy experimenting with e

This job is with our partner Micro1 Scope of Work Diagnose and resolve common hardware and software issues across Windows, Mac, and Linux environments, focusing on real-world troubleshooting scenarios. Document incident details, troubleshooting steps, and resolutions with clarity and precision using ticket management systems (ITSM). Utilize networking knowledge (TCP/IP, DNS, VPN) to resolve connectivity and configuration incidents. Support non-technical users by providing clear, empathetic communication and step-by-step technical guidance. Contribute detailed, scenario-based examples and process documentation that reflect best practices in IT support. Ensure all input and feedback is well-documented for AI training and continuous improvement purposes. Collaborate asynchronously within a remote engagement model, delivering high-quality, written and verbal feedback. Preferred Qualifications Minimum of 3 years’ experience providing Tier 2/3 IT support in diverse operating system and network environments. Deep familiarity with troubleshooting hardware, software, and networking issues, including root cause analysis. Proficiency in documenting technical incidents and resolutions using ITSM or similar ticketing platforms. Strong written and verbal communication skills, with a focus on supporting non-technical end users. Certifications such as CompTIA A+, CompTIA Network+, or ITIL Foundation are advantageous. Demonstrated ability to contribute to technical process documentation and knowledge bases. Proactive, detail-oriented, and comfortable participating in remote, independent project engagements.

Staff Embedded SW/FW Engineer (Bringup) Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. Job Summary We have an exciting opportunity to be part of a collaborative, cross-functional development team developing C code used to validate cutting-edge, high-performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Bringup team, you will be involved with bringing first silicon to life, developing code primarily in C to configure and exercise systems and sub-systems on new silicon devices, and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. The Team The Post-Silicon Bringup team sits within the Architecture and Validation team, we are responsible for bringup and validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and supporting the Silicon Characterisation team. Respons

About the Team OpenAI's Industrial Compute organization is building the world's most advanced AI infrastructure ecosystem. Through a combination of strategic partnerships and self-built campuses, we are scaling the compute, storage, and networking platforms that power frontier AI training and inference. The Scaling Analytics team builds the data and software systems that help Industrial Compute understand, plan, and operate infrastructure at global scale. We work across capacity, hardware, storage, infrastructure software, and operational systems to connect fragmented sources of infrastructure data and make that information reliable and usable for engineering and planning. As OpenAI's infrastructure footprint grows, CPU and storage data increasingly spans internal platforms, vendor systems, APIs, databases, object storage, capacity management systems, and operational tooling. Building reliable connections across these environments is critical to understanding available capacity, utilization, fleet state, and infrastructure growth. About the Role We are seeking a Data Engineer to build the data systems and integrations that connect OpenAI's CPU, storage, and supporting infrastructure platforms. This role sits at the intersection of data engineering and backend software engineering. Rather than focusing primarily on traditional analytical pipelines, you will build the software and integrations required to collect, normalize, and make infrastructure data available across a heterogeneous set of systems. CPU and storage data may originate from internal infrastructure platforms, vendor APIs, databases, object storage, capacity systems, and operational services. You will determine how to reliably connect these systems and where those integrations should live—whether within an existing infrastructure service, an orchestration framework, a scheduled workload, or a purpose-built application. You will work closely with Infrastructure Engineering, Capacity Engineering, Storage,

About Team Our Robotics team is focused on unlocking general-purpose robotics and advancing toward AGI-level intelligence in dynamic, real-world environments. Working across the full model and systems stack, we integrate cutting-edge hardware and software to explore a broad range of robotic form factors. We strive to seamlessly blend high-level AI capabilities with the physical constraints of real-world systems to improve people’s lives. About the Role We’re looking for a Technical Program Manager to own and scale the systems that power robotic data acquisition across our development and evaluation environments. This role sits at the intersection of Robotics Engineering, Operations, and Infrastructure, ensuring that DAQ stations and associated workflows reliably produce high-quality data for model training and evaluation. You will drive end-to-end execution of complex, cross-functional programs that integrate robotic platforms, sensing systems, operator tooling, and data pipelines into cohesive, production-ready systems. Success in this role requires strong systems thinking, operational rigor, and the ability to translate ambiguous research needs into scalable infrastructure. In this role you will: Own DAQ Program Delivery Lead the roadmap, execution, and scaling of robotic DAQ systems, ensuring alignment with research, engineering, and operational priorities. Drive Cross-Functional Integration Coordinate across robotics hardware, software, infrastructure, and operations teams to deliver tightly integrated, deployment-ready data collection systems. Operationalize Data Collection Systems Translate experimental and research workflows into repeatable, scalable DAQ processes with clear SLAs, metrics, and reliability targets. System Readiness & Deployment Ensure DAQ stations (robots, sensors, compute, operator interfaces) are fully integrated, validated, and ready for production use across multiple sites. Program Execution & Risk Management Build and manage detai

Job Details: Job Description: We are seeking an experienced Analog Design and Infrastructure DA Manager to lead the development, deployment, and governance of analog/mixed-signal design environments and CAD infrastructure. This role owns EDA tool ecosystems, PDK integration, compute infrastructure, design data governance, and tapeout manifest management to ensure high productivity, reproducibility, and audit readiness across silicon programs..The ideal candidate combines deep analog/mixed-signal design flow and e-test structure development expertise with strong infrastructure leadership and disciplined configuration/data management practices. Key Responsibilities-1. Analog Design Environment and Flow Management-Own and maintain analog and mixed-signal design flows using platforms such as Virtuoso ,Develop and maintain schematic, layout, verification, and extraction flows (LVS, DRC).Support simulation environments including HSPICE, Corner analysis.Drive automation and methodology improvements to reduce turnaround time and increase design robustness. 2. Infrastructure and Compute Management Oversee Linux-based DA infrastructure including compute farms, storage systems, and license servers (FlexLM). Manage LSF/grid environments and job scheduling systems. Ensure scalability, system monitoring, high availability, and performance optimization. Partner with IT on hardware lifecycle planning, cloud integration, and disaster recovery. Maintain secure, access-controlled design environments aligned with IP protection policies. 3. Design Data, Manifest and Configuration Management Design Data Governance Manage large-scale analog design libraries, hierarchical database structures, and technology libraries. Define backup, archival, and retention policies for tapeout-critical data. Implement data integrity validation and corruption prevention controls. Oversee distributed stor