Layout Designer in India

... Address: #110/1, M Krishnappa Layout, Lalbagh Road, Bengaluru - 560027 Facility: KA QHSE Qualification: Post graduate Experience: 15 - 20 years Preferred Gender: FEMALE Source: Sodexo India | Job Code: IJP556621

... Address: #110/1, M Krishnappa Layout, Lalbagh Road, Bengaluru - 560027 Facility: KA HR Recruitments Qualification: Graduate Experience: 3 - 5 years Source: Sodexo India | Job Code: IJP560073

... Address: #110/1, M Krishnappa Layout, Lalbagh Road, Bengaluru - 560027 Facility: KA Office Food Ops Management Experience: 15 - 18 years Source: Sodexo India | Job Code: IJP562327

The Lead – Cell Design is responsible for developing and optimizing battery cell architectures—from electrode formulation and coating parameters to cell layout, electrolyte selection, and mechanical design—to achieve targeted performance, safety, cost, and lifecycle metrics across applications. Source: Adani Group | Job ID: 53011

The objective of the job is to handle project co-ordination with different EPCM- contractors, resolve technical queries, as per project specifications. Plan and track deliverables as per project planning. Knowledge of plant layout and piping concepts of stress analysis, optimize layout, contribute during model reviews, understanding of codes and standards, skill set of 3D-Model. Source: Adani Group | Job ID: 41654

... Address: No. 35 20th Main 1st cross BTM 1 stage next to Union Bank of India BTM layout Bangalore Facility: MOJO (Christ College Hostels) - FS Qualification: 12th Experience: 2 - 3 years Source: Sodexo India | Job Code: IJP565715

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. ASIC IP STA Engineer (6-10 Years) | DDR PHY / ONFI PHY / IO Expander Location: Bengaluru, India Experience: 6-10 Years Enducational Qualification : BE/B-Tech/M-Tech (EEE, ECE, Micron Electronics, VLSI) Key Requirements Member of the AMS IP Physical Design team , responsible for post-layout STA signoff and timing closure of high-speed interface IPs, with close collaboration across IP Design, SoC Synthesis, and SoC Physical Design teams throughout IP development and SoC integration. 6-10 years of experience in Static Timing Analysis (STA) with a proven track record of 4 &#43; successful tapeouts . Strong hands-on expertise with Cadence Tempus (preferred). In-depth experience in MMMC timing analysis and closure across functional, scan, MBIST, and other DFT modes. Experience working on high-speed Memory Interface IPs such as DDR PHY, ONFI PHY, IO Expander (IOE) , or similar high-performance interface designs. Strong understanding of timing constraints development, validation, and debug , including clocks, generated clocks, timing exceptions, and mode-specific constraints. Experience in Liberty (.lib) and ETM timing model generation, validation, correlation, and quality assessment . <span

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, focusing on achieving robust, high-performance and power-efficient designs

Silicon Physical Design Engineer Multiple roles across different levels Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, fo

Within Infrastructure Management Team the candidate is acting as single point of contacts for all business requirements linked to the Cloud. He/she is responsible for understanding current and future customer demand for services. He is preparing the CAB (change advisory board) The candidate must have significant experience in Cloud / SAAS / PAAS / Infrastructure / system integration/migration. Address: No.110/1 M Krishnappa Layout Lalbagh Road Facility: SBS IS&T Global SA SA Qualification: Graduate Experience: 10 - 15 years Source: Sodexo India | Job Code: IJP561563

Job Details: Job Description: We are seeking an experienced Analog Design and Infrastructure DA Manager to lead the development, deployment, and governance of analog/mixed-signal design environments and CAD infrastructure. This role owns EDA tool ecosystems, PDK integration, compute infrastructure, design data governance, and tapeout manifest management to ensure high productivity, reproducibility, and audit readiness across silicon programs..The ideal candidate combines deep analog/mixed-signal design flow and e-test structure development expertise with strong infrastructure leadership and disciplined configuration/data management practices. Key Responsibilities-1. Analog Design Environment and Flow Management-Own and maintain analog and mixed-signal design flows using platforms such as Virtuoso ,Develop and maintain schematic, layout, verification, and extraction flows (LVS, DRC).Support simulation environments including HSPICE, Corner analysis.Drive automation and methodology improvements to reduce turnaround time and increase design robustness. 2. Infrastructure and Compute Management Oversee Linux-based DA infrastructure including compute farms, storage systems, and license servers (FlexLM). Manage LSF/grid environments and job scheduling systems. Ensure scalability, system monitoring, high availability, and performance optimization. Partner with IT on hardware lifecycle planning, cloud integration, and disaster recovery. Maintain secure, access-controlled design environments aligned with IP protection policies. 3. Design Data, Manifest and Configuration Management Design Data Governance Manage large-scale analog design libraries, hierarchical database structures, and technology libraries. Define backup, archival, and retention policies for tapeout-critical data. Implement data integrity validation and corruption prevention controls. Oversee distributed stor

Roles & Responsibilities Displays structured problem solving, application of right tools &amp; techniques to solve open ended problems, Creates productized analytics solutions or frameworks independently. Understand Business &amp; product problems and come up with deep data backed solutions. Root cause analysis and Deep dive analysis of certain product problems Running and maintaining the reporting system, presenting insights at a weekly forum Building templates, dashboards in Power BI, Gsheets for operational and management reporting Data extraction as per business request for Ad hoc analysis Business analysis and understanding Evaluating metrics to be tracked as per business goals, exploring other available metrics for deeper understanding of product performance Work in a fast-moving environment, across multiple projects with varying levels of complexity and detailing Desired Skills and Experience: 3 - 5 years working with large data sets and conducting quantitative analysis Some understanding of Statistics and prior experience of building statistical models (e.g. hypothesis testing, product experimentation, A/B Testing, regressions). Excellent knowledge SQL and intermediate knowledge of data manipulation language such as R/Python Previous experience with working on ecommerce funnels, retention Ability to think through product and business metrics to assess product features Knowledge of business modelling and basic knowledge of financial metrics, would be a bonus Quick learner and ability to work in dynamic work environment Team player and comfortable interacting with people from multiple disciplines Established expertise in designing new dashboards, identifying the right metrics, layout; displays proficiency in building dashboards on Power BI using best practices and intuitive Qualifications Bachelor’s in engineering, Computer Science, Economics, Statistics, or related discipline from a reputed institute ...........................

Role: Network Engineer Location: Gurgaon Graviton is a privately funded quantitative trading firm striving for excellence in financial markets' research. We are seeking a Network Engineer for our team in Gurgaon. Graviton trades across a multitude of asset classes and trading venues using a gamut of concepts and techniques ranging from time series analysis, filtering, classification, stochastic models, pattern recognition to statistical inference analysing terabytes of data to come up with ideas to identify pricing anomalies in financial markets. Key Responsibilities Design, deploy, operate, and troubleshoot low-latency network infrastructure used by trading firms. Manage connectivity to global stock exchanges, brokers, market-data providers, and ISPs. Build and maintain colocation infrastructure including routers, switches, Layer-1 devices (added advantage), structured cabling and cross connects. Configure and support Cisco Nexus, Arista and similar platform devices. Design and troubleshoot Layer 2 and Layer 3 networks including: VLANs, VRFs, BGP, OSPF, Static routing, PIM, IGMP, Multicast, SSM, ACLs and QoS. Troubleshoot packet loss, multicast issues, duplicate packets, IGMP/PIM and multicast/BGP routing. Monitor and optimize latency, jitter, packet loss, interface errors, congestion, and network performance. Work with ultra-low-latency technologies including: Cut-through switching, Layer-1 switches, FPGA-based network devices, Kernel-bypass networking, ExaNIC/Solarflare NICs, Hardware timestamping. Configure and troubleshoot PTP and clock synchronization infrastructure. Perform server and network equipment installation in exchange and third-party data centres. Manage rack layout, patching, cable optimization, optics, DACs, cross-connects, and inventory. Coordinate network changes with exchanges, telecom providers, brokers, vendors, and data-centre teams. Plan and execute production changes during approved maintenance windows. Perform pre-change validation, c

Instawork is on a mission to create meaningful economic opportunities for skilled hourly professionals in communities around the globe. Our AI-powered labor marketplace helps local businesses scale, and enables global technology companies to push the frontiers of robotics and AI. Backed by world-class investors like Benchmark, Spark Capital, Craft Ventures, Greylock, Y Combinator, and others, we’re looking for exceptional talent to reimagine the way the world works. About the Role We are seeking a proactive, detail-oriented, and high-energy Office Coordinator to oversee the day-to-day functions, facilities, and workplace culture of our Bangalore offices . Reporting directly to the Office Manager, you will be the heartbeat of our local workspace—ensuring a clean, seamless, and highly productive environment for our team. If you are a collaborative problem-solver who thrives on operational efficiency, vendor management, and creating an amazing workplace experience, we want to hear from you! Working days - 6 days/week Key Responsibilities 🏢 Facilities & Office Operations Daily Functions: Own the upkeep of common areas, workspaces, and conference rooms, ensuring all furniture and audio/video (AV) equipment are fully operational. Vendor & Supply Management: Proactively manage relationships with external service providers (property management, furniture vendors, snack/catering programs, custodial services, etc.) and keep office supplies fully stocked. Ticketing & Support: Provide timely, high-quality responses to internal service requests assigned to the facilities queue. Space Planning: Assist the Office Manager with employee seating arrangements, desk allocations, and office layout planning. Cross-Functional Support: Coordinate with onsite facility staff and address ad hoc projects directed by the IT, People (HR), and Finance teams as aligned with the Office Manager. 🎉 Culture & Employee Engagement Cultural Stewardship: Act as a culture champion by supp

The Mine Surveyor is responsible for conducting precise surveys and measurements to support the safe and efficient operation of the mine. This includes developing and maintaining accurate mine plans and layouts, monitoring geological features, and ensuring compliance with relevant regulations. The role requires collaboration with engineers, geologists, and management to provide critical data for mine planning, development, and safety. Source: Adani Group | Job ID: 58105