Staff Engineer Code Generation in Bengaluru

Secure Every Identity, from AI to Human Identity is the key to unlocking the potential of AI. Okta secures AI by building the trusted, neutral infrastructure that enables organizations to safely embrace this new era. This work requires a relentless drive to solve complex challenges with real-world stakes. We are looking for builders and owners who operate with speed and urgency and execute with excellence. This is an opportunity to do career-defining work. We're all in on this mission. If you are too, let's talk. Staff Product Designer — AX & Growth (DLG) About the Role Auth0, part of Okta, is redefining identity for a world where users aren't only human. AI agents are beginning to sign up, authenticate, and act autonomously — and Auth0 is building the infrastructure and experience layer for that shift. This role is a foundational design hire on Auth0's India Design Team, part of the global design team. Working at the frontier of Agent Experience (AX) : designing for a largely headless, invisible-UI world where the "user" is often code acting with intent, not a person. You'll join a small pod of PMs and engineers actively defining Auth0's agentic vision from scratch — there's no existing pattern library, so you'll help create it: how agents sign up, authenticate, execute tasks, and how humans stay in control without micromanaging them. Alongside this, you'll own signup and onboarding design for a new customer: the AI-powered developer, whose workflows involve agents and automated tooling from day one. The same instincts that build trust for a human overseeing an agent also build trust for a developer signing up for a self-serve product. We're looking for a self-starter who generates their own hypotheses and builds the roadmap as they go. What You'll Do Agent Experience (AX) - Shape Auth0's agentic vision alongside a small, fast-moving team of PMs and engineers. - Define the "what" for agents — interaction models for sig

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE Team lead for a group of engineers with responsibility for Linux and VMWare initiator stack behavior as well as Fibre Channel and NIC drivers on Pure storage array. WHAT YOU'LL DO The Kernel and Driver development team is responsible for several areas Working for a team that deals primarily in various storage area network protocols such as Fiber Channel and Ethernet. On the initiator side, the team will be responsible for Linux initiator behavior attached to Flasharray. Focus is on NVME (ROCE, FC, TCP/IP) but also includes FC-SCSI (FCP) and iSCSI interfaces. This includes software development/fixes for Linux initiator stack, debugging initiator problems, and creating compatibility documents for Purity. For VMWare, focus is on debugging issues with VMWare as an initiator, and creating compatibility documentation. For FibreChannel and NIC Drivers, focus is responsibility for FC-SCSI driver stack for storage side and responsibility for NIC drivers on networking side. This includes responsibility for related code, utilities, enhancements supporting RAS, as well as debugging failures found internally and in the field. Maintain Linux kernels for internal testing Documenting supported configurations for customers Responsibility for evaluating Linux initiator behavior and optimizing for Pure Storage Flasharray. This includes correctness as well as optimizing for performances. Will contribute bug fixes and enhancemen

Here's a summary of the role: Do you love building scalable cloud platforms and solving complex engineering problems with modern technologies? As a Senior Software Engineer at Diligent, you'll design and deliver high-performing , serverless applications that power our global SaaS platform. You'll work extensively with TypeScript, Node.js, AWS, and event-driven microservices, owning services from design to deployment and production monitoring. This is an opportunity to influence technical decisions, mentor engineers, and explore how AI can transform software development and engineering productivity. If you're passionate about cloud-native architectures, distributed systems, and building software that scales to millions of users, we'd love to meet you. Here's a breakdown of what you'll do (not all of it, just the important stuff): Design and build scalable backend services and event-driven microservices using TypeScript and AWS. Develop secure APIs and integrations that power reporting, analytics, and dashboard experiences. Build and maintain serverless solutions using AWS services such as Lambda, EventBridge , SQS, and DynamoDB. Drive engineering excellence through testing, observability, automation, and production readiness practices. Contribute to infrastructure-as-code and CI/CD pipelines using AWS CDK and modern DevOps practices. Mentor engineers, participate in architecture discussions, and champion the use of AI tools to improve development efficiency. These are the essentials you'll need to get an interview: 6-8 years of professional software engineering experience. Strong experience with TypeScript, Node.js, and modern backend development patterns. Hands-on experience building cloud-native applications on AWS. Strong understanding of serverless architectures and event-driven microserv

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE As the Team Lead for Initiator & Protocol Engineering, you will spearhead the critical bridge between our industry-leading FlashArray and the Linux/VMWare ecosystems. You will drive the performance and reliability of our storage protocol stacks—spanning NVMe over Fabrics and Fibre Channel—ensuring Pure Storage remains the gold standard for enterprise connectivity. Collaborating closely with cross-functional hardware and software teams, you’ll mentor a high-caliber engineering squad to solve complex kernel-level challenges and influence the global Linux upstream community. WHAT YOU'LL DO Own the Protocol Lifecycle: Lead the development, maintenance, and optimization of Linux and VMWare initiator stacks (NVMeoF, FC-SCSI, iSCSI) and target drivers to ensure seamless, high-performance integration with Pure FlashArray. Drive System Resilience: Architect enhancements for Fibre Channel and NIC driver stacks that improve RAS (Reliability, Availability, and Serviceability), specifically focusing on multipathing logic and link health monitoring. Technical Leadership & Mentorship: Guide a team of senior and junior engineers through complex project deliveries, conducting deep-dive code reviews and setting the technical bar for C/C++ and Python development within the kernel space. Solve the Impossible: Act as the final escalation point for the most challenging system-level bugs found in the field or internal testing, u

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE Join the FlashArray team to build high-performance, resilient storage software that powers mission-critical applications worldwide. As a core member of an agile engineering group, you will design and deliver zero-downtime algorithms that directly shape our enterprise storage and public cloud offerings. In this role, you will partner closely with global systems engineers and product teams to translate complex technical challenges into scalable, real-world solutions. Your work will directly impact how thousands of global enterprises manage, protect, and scale their data seamlessly. WHAT YOU’LL DO Design & Deliver Resilient Systems: Architect and implement high-performance algorithms for enterprise storage products, ensuring platform reliability, end-to-end delivery from concept to release, and six-nines availability. Expand Cloud Architecture: Extend core platform capabilities into public cloud environments (such as AWS), driving performance and agility for both traditional IT and cloud-native applications. Drive Problem Solving & Quality: Analyze and resolve complex systems software challenges, optimizing storage internals and contributing to continuous continuous platform upgrades. Collaborate & Mentor: Partner with multidisciplinary engineering peers to review code, refine architecture, and maintain high engineering standards across distributed software projects. WHAT YOU BRING Systems Programming Exp

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. ASIC IP STA Engineer (6-10 Years) | DDR PHY / ONFI PHY / IO Expander Location: Bengaluru, India Experience: 6-10 Years Enducational Qualification : BE/B-Tech/M-Tech (EEE, ECE, Micron Electronics, VLSI) Key Requirements Member of the AMS IP Physical Design team , responsible for post-layout STA signoff and timing closure of high-speed interface IPs, with close collaboration across IP Design, SoC Synthesis, and SoC Physical Design teams throughout IP development and SoC integration. 6-10 years of experience in Static Timing Analysis (STA) with a proven track record of 4 &#43; successful tapeouts . Strong hands-on expertise with Cadence Tempus (preferred). In-depth experience in MMMC timing analysis and closure across functional, scan, MBIST, and other DFT modes. Experience working on high-speed Memory Interface IPs such as DDR PHY, ONFI PHY, IO Expander (IOE) , or similar high-performance interface designs. Strong understanding of timing constraints development, validation, and debug , including clocks, generated clocks, timing exceptions, and mode-specific constraints. Experience in Liberty (.lib) and ETM timing model generation, validation, correlation, and quality assessment . <span

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. What Makes This Opportunity Unique At Micron, we're not just offering a job; we're presenting a chance to be part of a team that develops the future of memory and storage solutions. As a Staff Engineer, ASIC STA in our Bengaluru office, you will have the opportunity to work with powerful technology and contribute to highly innovative projects. Your work will help us deliver flawless results and uphold our world-class standards! Job Responsibilities Proficient at Synthesis, Static Timing Analysis (STA), and Logic Equivalence Checking (LEC) Ability to understand and integrate new mixed signal complex IPs Expertise in developing constraints and timing models Manage synthesis to timing closure, ensuring all checks for silicon success Experience with hierarchical designs involving high-frequency clocks Proficient with scripting, automation, and EDA tools Proficiency with AI and AI-enabled workflows Solid understanding of low power builds involving multiple power domains Identify and meet requirements for critical paths of multi-GHz builds Collaborate effectively in multi-functional and globally dispersed teams Requirements M.S./M.Tech, BS/BE in Electronics or related field Minimum of 6&#43; years of relevant experience Proven ability to successfully implement complex builds Ambitious and determined to compete at a global level <

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we build open, state of the art compute for real workloads and real developers.You will own CPU core‑level verification, shaping how our out‑of‑order RISC‑V CPUs behave in silicon. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring 8+ years in CPU verification or closely related digital design. You know high‑performance out‑of‑order CPU microarchitecture in depth. You work comfortably with RTL, waveforms, logs, and complex debug scenarios. You communicate clearly across design, DV, emulation, and post‑silicon teams. What We Need Plan and drive functional verification for CPU core features and complex microarchitectural scenarios. Develop UVM, assembly, and C/C++ based stimulus, functional models, and coverage for ISA, RISC-V extensions, and un-core components. Debug simulation and emulation regressions using RTL understanding, waveforms, and logs to identify and resolve issues efficiently. Build and enhance coverage models, testbenches, and debug infrastructure to improve verification quality and coverage closure. Collaborate with design, validation, and

For over 20 years, Smartsheet has empowered teams to manage work seamlessly and scale solutions smarter. Now, in our most ambitious chapter yet, we are uniting human teams with AI agents. By orchestrating the work agents do best, automating manual tasks and uncovering insights at scale, we create the space for people to focus on what truly matters: judgment, creativity, and big thinking. That is magic at work, and it’s what we show up for every day. You Will: Data Architecture and Design: Designing and overseeing the architecture of scalable and reliable data platforms, including data pipelines, storage solutions, and processing systems Data Modelling and Management:Developing and implementing data models, ensuring data quality, and establishing data governance policies Data Pipeline Development: Building and optimising data pipelines for ingesting, processing, and transforming large datasets from various sources Performance Optimisation: Identifying and resolving performance bottlenecks in data pipelines and systems, ensuring efficient data retrieval and processing Technology Evaluation and Innovation: Staying abreast of emerging data technologies and exploring opportunities for innovation to improve the organisation’s data infrastructure Troubleshooting and Problem Solving: Diagnosing and resolving complex data-related issues, ensuring the stability and reliability of the data platform Data Security and Compliance: Implementing data security measures, ensuring compliance with data governance policies, and protecting sensitive data Perform other duties as assigned You Have: Bachelor’s or Master’s degree in Computer Science, Engineering, or a related field. 10+ years of experience in data engineering or a similar role. Enterprise SaaS software solutions with high availability and scalability Solution handling large scale structured and unstructured data from varied data sources Experience in building and maintaining data platform systems such as distributed compute,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Firmware Engineer at Micron Technology, Inc., you will build groundbreaking high-performance controller firmware for volatile and non-volatile memory systems. You will assist in the evaluation, creation, build, bench testing, debugging, and failure analyzes of firmware for new high-performance memory controllers and Solid State Drives (SSD) that will improve performance, while reducing power, latency and SoC (System on Chip) complexity for the target sectors. You can expect to partner multi-disciplinary Engineers seek multi-functional product development issues. You will triage failures, file bug reports, and help the development teams with isolating issues. Experience / Skills: 4&#43; Years of experience in managing the test development team within the storage domain. In depth knowledge and extensive experience with embedded firmware development Expertise in the use of scripting languages, programming tools and environments Extensive experience programming in Python Experience in the storage industry in SSD, HDD, storage systems, or a related technology Understanding of storage interfaces including ideally PCIe/NVMe, SATA, or SAS Experience with NAND flash and other non-volatile storage Ability to work independently with a minimum of day-to-day supervision Experience with team leadership and/or supervising junior engineers and technicians Ability to work in a multi-functional team and under the pressure of multiple priorit

Secure Every Identity, from AI to Human Identity is the key to unlocking the potential of AI. Okta secures AI by building the trusted, neutral infrastructure that enables organizations to safely embrace this new era. This work requires a relentless drive to solve complex challenges with real-world stakes. We are looking for builders and owners who operate with speed and urgency and execute with excellence. This is an opportunity to do career-defining work. We're all in on this mission. If you are too, let's talk. Job Overview: We are looking for a highly experienced Staff Engineer to join the FGA DevEx team and lead the evolution of our end to end developer experience across both OSS and SaaS. This team owns the SDKs in Go, JavaScript, .NET, Python, Java and other languages, along with CLI workflows, IDE integrations, GitHub automation, developer documentation, and release strategy. All development is done in the open as open source, and we actively welcome and review community contributions. Our guiding principle is One developer experience, many deployment models. As a Staff Engineer, you will define technical direction, ensure cross language consistency, influence API design in partnership with FGA Core, and raise the quality bar across all developer facing tooling. Responsibilities: Define and drive the technical direction for FGA DevEx , CLI, IDE integrations, and developer automation across OSS and SaaS. Lead architectural decisions for multi language SDKs in Go, JavaScript, .NET, Python, and Java, leveraging and evolving the SDK generator that forms the core of all clients. Own and evolve the SDK generator framework, templates, and wrapper patterns to ensure cross language consistency, configurability, and long term maintainability. Establish standards across SDKs for authentication flows such as client credentials, error mapping and handling, retry logic with appropriate rate limiting strategies, and method level configuration overrides. Ensure advanced SDK

Staff Engineer - Analog Layout — Bengaluru, India. Apply via Workday.

Staff Engineer - Analog Layout — Bengaluru, India. Apply via Workday.

STAFF Engineer -DEG Layout — Bengaluru, India. Apply via Workday.

STAFF Engineer -DEG Layout — Bengaluru, India. Apply via Workday.