Advanced Packaging Engineer

About the Role You will contribute to and own aspects of the Volantis A-0 and A-1 package. We are interested in both people with package design as well as package process development backgrounds Our end goal has challenges to overcome in warpage, CTE mismatch, thermomechanical aspects, assembly speed and more. We're building a wafer-scale package with both silicon and compound semiconductor dies sitting together at very high TDP. This creates both unique challenges and opportunities. The end result is breaking the memory wall, enabling a new era of AI, and a platform that scales another 1-3 orders of magnitude. What We Look For Ability to think from first principles about novel problems- not just applying existing solutions outside of their range of application. What works for 5x reticle platforms may not work for 56x reticle platforms Design or process development of complex packages Nice to Have: Experience with heterogeneous material assemblies Experience with high-TDP packages Experience with compound semiconductor assemblies Experience with co-packaged optics Ability to work with architects to co-design system architecture and package design Experience with interposer platforms such as CoWoS, CoWoS-L, CoWoS-R, EMIB, FoCoS, FoCoS-Bridge, etc Experience with flip-chip integration, especially mass reflow, TCB & LAB Experience with large scale (>50x50mm) substrates Compensation Package: Competitive Base salary + Significant Equity Stake. You'll be well compensated while also owning a piece of the outcome. California Pay Range: $250K-$400K