Advanced Design Engineer Jobs

About Hark Hark is an artificial intelligence company building advanced, personalized intelligence. One that is proactive, multimodal, and capable of interacting with the world through speech, text, vision, and persistent memory. We're pairing that intelligence with next-generation hardware to create a universal interface between humans and machines. While today's AI largely operates through chat boxes and decade-old devices, Hark is focused on what comes next: agentic systems that interact naturally with people and the real world. To get there, we're developing multimodal models and next-generation AI hardware together - designed from the ground up as a single, unified interface for a new era of intelligent systems. About the Role We are looking for an incredible Manufacturing Design Engineer to bridge the gap between design intent and the physical product at Hark. You will work with ID and PD, ensuring that what we conceive is built exactly as imagined at quality and scale. This is the role where craft meets constraint. You understand materials, processes and tolerances at a deep level, and you use that knowledge to protect the integrity of the design all the way through production. You've worked closely with factories, tooling engineers and supply chain partners, and you know how to navigate that world without compromising what matters. Responsibilities Partnering with industrial designers and mechanical engineers to translate design concepts into manufacturable products Owning design for manufacturability (DFM) across materials, finishes, tolerances and assembly processes Working directly with contract manufacturers, tooling vendors and supply chain partners to drive quality and consistency Identifying and resolving manufacturing risks early in the development cycle Maintaining design intent through mass production, managing deviations and approving samples Contributing to process improvements that raise the quality bar across Hark's hardware line Requirem

About Hark Hark is an artificial intelligence company building advanced, personalized intelligence. One that is proactive, multimodal, and capable of interacting with the world through speech, text, vision, and persistent memory. We're pairing that intelligence with next-generation hardware to create a universal interface between humans and machines. While today's AI largely operates through chat boxes and decade-old devices, Hark is focused on what comes next: agentic systems that interact naturally with people and the real world. To get there, we're developing multimodal models and next-generation AI hardware together - designed from the ground up as a single, unified interface for a new era of intelligent systems. About the Role You’ll drive the system-wide thermal architecture for our AI-centric consumer devices, from early concepts through detailed architecture and production validation. Balance performance, battery life, cost, and user comfort. Work hands-on across simulation, prototyping, and test to enable informed architecture analysis, proactively highlighting tradeoffs and opportunities. Collaborate closely with industrial design, mechanical, electrical, and software teams to converge holistic thermal solutions. Responsibilities Define and own the thermal architecture from early architecture & NPI through production, including foundational system architecture simulation & analysis, material selection, thermal solution design, and cost optimization. Translate product use cases and real-world usage profiles into thermal loading scenarios that drive early design iteration Conduct detailed thermal analysis at variable fidelity levels as needed - analytic analysis for team directional analysis, coarse analysis for quick iteration of parallel ideas, and detailed analysis for high fidelity studies. Design and build custom thermal test infrastructure and measurement methodologies tailored to each product program Partner cross-funct

About Hark Hark is an artificial intelligence company building advanced, personalized intelligence. One that is proactive, multimodal, and capable of interacting with the world through speech, text, vision, and persistent memory. We're pairing that intelligence with next-generation hardware to create a universal interface between humans and machines. While today's AI largely operates through chat boxes and decade-old devices, Hark is focused on what comes next: agentic systems that interact naturally with people and the real world. To get there, we're developing multimodal models and next-generation AI hardware together - designed from the ground up as a single, unified interface for a new era of intelligent systems. About the Role We're hiring a Product Design Engineer to help shape the physical form of our AI-powered devices. You'll work across the full product development cycle — concept sketches, CAD modeling, prototyping, and DFM — collaborating with electrical and ML engineers to design enclosures and mechanisms that accommodate complex sensor arrays, thermal systems, and compact compute modules. Responsibilities Lead mechanical design of core hardware (enclosures, structural components, flex assemblies, interconnects) from concept to production Convert industrial design intent into reliable, manufacturable, and precise engineering solutions, maintaining product vision and structural/functional performance Define and own specifications, tolerances, material selections, and 3D CAD across processes like injection molding, die casting, stamping, and CNC machining Drive Design for Manufacturability (DFM) and Design for Assembly (DFA) with manufacturing partners from early concept through production builds Use tolerance analysis, FEA, and DOE's to validate designs and resolve failure modes pre-assembly Collaborate with Industrial Design, Electrical Engineering, Acoustic Engineering, Reliability & Operations to unify design considerations (functionality, thermal

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. About the Role EnCharge AI is looking for a highly motivated and experienced Staff Physical Design Engineer to drive the physical implementation of our next-generation semiconductor chips. In this role, you will play a critical part in translating complex microarchitectures into high-performance, power-efficient silicon. Working closely with cross-functional teams, you will own block-level and top-level implementation using industry-standard EDA tools, tackle complex timing closure and power challenges, and guide designs all the way from netlist to successful foundry tapeout. Key Responsibilities Drive block-level and top-level physical design, including floor-planning, placement, clock tree synthesis (CTS), and routing. Achieve aggressive timing, power, and area (PPA) targets through advanced timing closure techniques. Perform power grid verification and manage electromigration and IR drop (EM/IR) analysis and resolution. Develop and maintain automation scripts (Tcl/Python) to streamline design flows and methodologies. Collaborate with physical verification and foundry teams to ensure design rule compliance and successful tapeout execution. Qualifications and Requirements Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 10–15 years of dedicated experience in physical design. Strong understanding of EDA implementation flows

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Job Title: Senior Physical Design Engineer Experience: 4–7 Years Focus: Block-Level RTL-to-GDSII & PPA Optimization Location: Bangalore Hybrid The Role We are looking for a high-energy, technically curious Physical Design Engineer to join our advanced silicon team. This isn't a role for someone who wants to just "push buttons" on a vendor flow. We need a driver—someone with 4–6 years of experience who has lived through the trenches of quality tape-outs and is hungry to take full ownership of complex partitions. You will be expected to work with a high degree of independence, using your analytical skills to bridge the gap between a standard recipe and a world-class PPA result . You should be comfortable following expert lead direction while maintaining the "question the status-quo" mindset when you see a more efficient path. Key Responsibilities Partition Ownership: Lead the physical implementation of complex blocks from Synthesis and Floor-planning through to CTS, Routing, and Sign-off. PPA Recipe Development: Don't just run the flow—optimize it. You will perform deep-dive analysis on timing paths, power profiles, and congestion to derive custom optimization strategies. Automation-First Mindset: Use Tcl and Python to automate repetitive tasks, build custom analysis scripts, and enhan

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Job Title: Principal Physical Design Engineer (RTL-to-GDSII) Experience: 14+ Years Technology Focus: Sub-5nm (3nm/2nm) Location: Bangalore Hybrid The Vision We are seeking a Principal Physical Design Engineer who thrives on complexity and rejects the "black box" approach to EDA tools. This role is for a First Principles thinker who questions the status quo. If a standard flow isn't yielding the desired PPA (Power, Performance, Area), you dive into the PDK, the tool algorithms, and the methodology to find a better way. You are responsible for transforming raw RTL into world-class silicon by eliminating systemic bottlenecks and building a scalable, predictable path to GDSII. Key Responsibilities Full-Flow Ownership: Lead the implementation of massive, high-speed blocks/SoCs from Synthesis through Sign-off using the Cadence Digital Suite . PPA Optimization: Push the theoretical limits of the PDK and tools. You will analyze and optimize the interplay between library cells, metal stacks, and tool engines to squeeze out every millivolt and picosecond. Methodology & Scalability: Build and refine a "Push-Button" style execution methodology that is robust, repeatable, and minimizes manual "human-in-the-loop" iterations. Cross-Functional "Left-Shift": Collaborate with RTL, Architecture, and DFT te

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are seeking a highly skilled Physical Design Engineer with deep expertise in physical design and methodology. This individual contributor role sits within our physical design team and is central to delivering power, performance, and area (PPA) optimized datapath and interconnect solutions for next-generation AI accelerators. You’ll work closely with RTL designers to define and execute on physical design strategies. You will develop tools, flows and methodologies to increase team productivity. Your work will directly impact silicon’s performance and cost efficiency, as well as the team’s execution velocity and quality. In this role, you will: Develop, build and own tools, flows and methodologies for physical implementation Own physical implementation of floorplan blocks from floorplanning to final signoff Collaborate with RTL designers to drive optimal block implementation solutions Analyze and optimize design for timing, power, and area trade-offs, working in collaboration with EDA vendors and ASIC partners Qualifications: BS w/ 4+ or MS with 2+ years or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development Demonstrated success in taping out complex silicon designs Hands-on experience with block physical implementation and PPA convergence Strong coding experience with python, bazel, TCL Strong experience building physical design tools, flows and methodologies Strong understanding of microarchitecture, RTL design,

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced, hands-on RTL engineer with deep packet-networking and interconnect expertise to own critical on- and off-chip communication components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip fabrics connecting high-bandwidth compute, memory, and I/O subsystems, as well as purpose-built off-chip interfaces and protocols that enable custom computing at scale. The ideal candidate has recently owned production RTL for networking or packet-switched datapaths such as Ethernet switches, NICs, SmartNICs, network accelerators, RDMA/RoCE systems, NoCs, or custom scale-up/scale-out fabrics. This is a senior engineering role with broad technical ownership and substantial direct RTL work. You will drive designs from requirements and performance analysis through microarchitecture, SystemVerilog implementation, verification closure, physical design convergence, silicon bring-up, and production readiness. You will also plan and oversee the work of junior engineers and help develop productive engineering relationships with external partners. In this role, you will: Own the microarchitecture, RTL design, and delivery of major packet-based interconnect and networking components, including NoC fabrics, switches, routers, bridges, protocol adapters, arbiters, queues, schedulers, buffers, and traffic-management logic. Design mechanisms for routing, arbitration, ordering, flow con

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Lead the architecture, design, integration, and silicon validation of complex analog and mixed-signal circuits for advanced DRAM products, including amplifiers, comparators, references, LDOs, charge pumps, oscillators, DLLs, I/O circuits, and on-chip monitors. Drive development of custom analog and digital IP from concept through tape-out, silicon bring-up, and production. Define architectures and design methodologies to optimize power, performance, area (PPA), reliability, yield, and manufacturability. Lead verification, modeling, parasitic analysis, silicon correlation, and design signoff across PVT and reliability corners. Guide physical implementation, including floorplanning, matching, placement, routing, and reliability-aware layout practices. Collaborate with Product, Process, Test, Probe, Assembly, and Manufacturing teams to ensure successful product qualification and high-volume production. Drive design quality, standardization, and continuous improvement through advanced CAD, modeling, automation, and verification methodologies. Mentor and develop engineering talent while providing technical leadership across projects and product generations. Drive innovation through reusable IP development, patents, technology roadmaps, and differentiated circuit architectures. Leverage engineering tools powered by AI and agentic AI workflows to improve build efficiency, accelerate verification, optimize PPA, and reduce p

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Job Title: Staff/ Senior Staff Physical Design Engineer (Technical Lead) Experience: Staff 8-10 years Senior Staff 11-13 years Location: Bangalore Hybrid/Remote or Remote in India The Role We are seeking a high-impact Staff/ Senior Staff Physical Design Engineer to serve as a Technical Lead for our next-generation silicon products. This is a "player-coach" role designed for a versatile expert who is equally comfortable architecting a convergence strategy as they are mentoring a small team of engineers. You will own the physical delivery of a major sub-chip or complex block, pushing the absolute limits of PPA (Power, Performance, Area) . As a Staff/Senior Staff lead, you are expected to be the "anchor" of the project—assertive in your decision-making, highly analytical in your debugging, and adept at managing stakeholders to ensure we hit our tape-out milestones without compromise. Key Responsibilities Technical Leadership: Lead a small team of PD engineers, providing technical direction, workload management, and architectural oversight for a sub-chip or partition. SOC clocking , FEV/VCLP specialized skills are preferred. Complex Block/Sub-chip Ownership: Take personal hands-on ownership of the most critical, high-congestion, or timing-critical blocks in the desi

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. SUMMARY: As a Design Engineer at Micron Technology, Inc., you will be responsible for designing and analyzing digital and analog circuits used in the development of memory products. We are engaged in developing groundbreaking silicon-to-systems solutions – right from technology development and advanced memory designs to product development, systems design and validation resulting in world class memory solutions. In this position, you will collaborate with Micron’s various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction. Responsibilities: Contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits. Parasitic modeling and assisting in design validation, reticle experiments and required tape-out revisions. Overseeing and managing the layout process including floor-planning, placement, and routing. Performing verification processes with modeling and simulation using industry standard simulators. Contributing to cross group communication to work towards standardization and group success. Working with Marketing, Probe, Assembly, Test, Pro

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Design and CAD Enablement Own the development, deployment, and support of scalable CAD tools, automation frameworks, design flows, and methodologies for NAND, DRAM, HBM, SoC, mixed-signal, and other advanced semiconductor products. Develop, improve, and maintain infrastructure for circuit build capture, layout, simulation, characterization, implementation, physical verification, and signoff workflows. Create robust software and scripts using Python, Tcl, SKILL, Shell, Perl, C/C++, Java, Lisp, or related languages to automate engineering workflows, analytics, and quality checks. Evaluate and integrate advanced EDA technologies, AI-assisted engineering solutions, and emerging methodologies to improve productivity, scalability, and silicon quality. Validated ability to demonstrate AI‑assisted (vibe) coding techniques to improve efficiency or automate design and analysis methodologies Leverage AI tools to automate the tools and workflow Applying Artificial Intelligence in workflows to improve build efficiency undefined undefined Lead implementation and signoff activities across physical design, static timing analysis, and design for test for complex digital, memory, SoC, or mixed-signal products. Drive floor planning, power planning, placement, clock tree synthesis, routing, optimization, timing closure, and physical verification to meet power, performance, area, reliability, and sche

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron’s Heterogeneous Integration Group (HIG) is shaping the future of AI and accelerated computing by developing advanced memory solutions! The team focuses on designing and optimizing High Bandwidth Memory (HBM) products for AI/ML, high-performance computing (HPC), and data-centric systems, collaborating across global engineering and product teams to deliver industry-leading performance, power efficiency, and reliability! HBM product family is growing due to high demand from industry-leading semiconductor companies. As an HBM Design Engineer, you will work closely with cross-functional teams including Design Engineering (DE), Product Engineering (PE), Process Integration, Packaging, and Technology Development (TD) to analyze and resolve silicon issues across HBM products . You will collaborate with architecture to understand new or updated specification requirements and contribute to the implementation, verification, and maintenance of design updates , supporting both silicon release and ongoing product lifecycle needs. This role requires strong technical execution and the ability to independently drive complex issues to closure. Responsibilities Design Support: Work on HBM product design and support sustaining design maintenance (ECOs/spec changes). Silicon Debug: Own end-to-end debug of silicon, system, and customer issues, driving root-cause analysis and resolution. Cross-Functional Collaboration: Work closely with DE, PE, TD, and system teams

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are building innovative physical design capabilities that help bring advanced semiconductor products from concept to silicon. Our team collaborates across design, verification, and manufacturing disciplines to deliver high-quality solutions using leading-edge technologies. We value technical excellence, continuous learning, and a culture of teamwork and innovation. As a Physical Design Engineer, you will play a key role in driving semicustom physical implementation from netlist handoff through tapeout. You will work closely with cross-functional engineering teams to optimize design quality, achieve physical signoff, and support successful product delivery in advanced technology nodes. Responsibilities: Execute the semi-custom physical design flow from netlist handoff through physical verification and tapeout Develop and maintain floorplans, placement, routing, power distribution networks (PDN), and physical design constraints Perform DRC, LVS, parasitic extraction, and physical signoff activities Analyze and resolve timing, signal integrity, electromigration, IR drop, reliability, and manufacturability issues Partner with cross-functional teams to drive design closure, debug issues, and support tapeout readiness Minimum Qualifications: Bachelor's or Master's degree in Electrical Engineering or a related field Experience in VLSI physical design, semiconductor lay

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, we design the memory that moves the world — from advanced DRAM to complete silicon-to-systems solutions! Our design teams work at the leading edge of memory technology, and we collaborate across the globe to turn ambitious ideas into world-class products. If you want your work to show up in the devices billions of people rely on, this is the place to do it. As a Staff Design Engineer on our DRAM team, you'll shape the circuits at the heart of our next memory generations. You'll own design decisions that directly affect cost, quality, reliability, and time-to-market, and you'll partner with talented engineers across design, verification, product, and manufacturing. This is a role for someone who enjoys working close to silicon and wants real ownership over the products they help create. Responsibilities: Design, lay out, and optimize Memory, Logic, and Analog circuits for new memory products Handle parasitic modeling and support design validation, reticle experiments, and tape-out revisions Oversee the layout process, including floor-planning, placement, and routing Run verification through modeling and simulation using industry-standard simulators Partner with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering to ensure manufacturability, and use Generative AI tools to speed up design, analysis, and documentation while owning correctness and signoff Minimum Qualifications: Bachelor's degree in Electrical