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Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Manager of the CMP area for the Advanced Technology Engineering team at Micron Technology, Inc., you will build and develop an elite team. Your team will drive new product introduction and ramp at our newest memory fab. This brand-new site in Boise, ID will combine technology development and manufacturing to transfer groundbreaking products from R/D into manufacturing. Your team will engage on Micron’s groundbreaking products from early in the development stage and support them all the way through customer qualification. Your objective is to use global internal and external resources to enable equipment and yield performance to plan. Responsibilities: Ensure all required safety training is completed and work is conducted in accordance with Micron safety policies while promoting a positive work environment. Hire, develop, mentor, and manage a team of highly capable process engineers. Support the qualification of a new innovative processing facility. Provide regular feedback to your team members on performance and career development. Engage with suppliers to develop the process and equipment needed to meet Micron’s technology roadmap. Collaborate with the Technology Development team to ensure successful transfer and ramp of product yield and quality. Engage with other Manufacturing teams and lead w

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are building innovative physical design capabilities that help bring advanced semiconductor products from concept to silicon. Our team collaborates across design, verification, and manufacturing disciplines to deliver high-quality solutions using leading-edge technologies. We value technical excellence, continuous learning, and a culture of teamwork and innovation. As a Physical Design Engineer, you will play a key role in driving semicustom physical implementation from netlist handoff through tapeout. You will work closely with cross-functional engineering teams to optimize design quality, achieve physical signoff, and support successful product delivery in advanced technology nodes. Responsibilities: Execute the semi-custom physical design flow from netlist handoff through physical verification and tapeout Develop and maintain floorplans, placement, routing, power distribution networks (PDN), and physical design constraints Perform DRC, LVS, parasitic extraction, and physical signoff activities Analyze and resolve timing, signal integrity, electromigration, IR drop, reliability, and manufacturability issues Partner with cross-functional teams to drive design closure, debug issues, and support tapeout readiness Minimum Qualifications: Bachelor's or Master's degree in Electrical Engineering or a related field Experience in VLSI physical design, semiconductor lay

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Own and drive custom analog and mixed-signal layout for critical LPDDR PHY blocks, including Datapath, bias networks, IO front ends, and reference circuits, ensuring robust operation across PVT, low noise coupling, and high matching accuracy 3-12 years of solid hands-on experience in custom analog and high-speed layout design, with proven expertise in implementing and delivering critical analog blocks and LPDDR/high-speed interfaces at advanced technology nodes Lead high-speed LPDDR (LPDDRx) interface layout execution , solving complex signal integrity challenges such as skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity in advanced nodes Architect and implement scalable array-based layout strategies for DQ/DQS byte lanes, CA lanes, and replica paths, ensuring strict symmetry, pitch matching, repeatability, and multi-channel scalability Drive integration of custom digital and mixed-signal blocks within the PHY (training logic, calibration engines, test/debug circuitry), ensuring optimal clocking, congestion management, and isolation from sensitive analog regions Lead layout-aware co-design with circuit teams , enabling early closure of timing, noise, IR, EM, and parasitic effects, and influencing design decisions from a layout perspective Establish robust power distribution, grounding, and isolation strategies , including guard rings, deep N-well usage, decoupling, and domain separation for

JLL empowers you to shape a brighter way . Our people at JLL are shaping the future of real estate for a better world by combining world class services, advisory and technology for our clients. We are committed to hiring the best, most talented people and empowering them to thrive, grow meaningful careers and to find a place where they belong. Whether you’ve got deep experience in commercial real estate, skilled trades or technology, or you’re looking to apply your relevant experience to a new industry, join our team as we help shape a brighter way forward. About JLL- We’re JLL—a leading professional services and investment management firm specializing in real estate. We shape the future of real estate for a better world by using the most advanced technology to create rewarding opportunities, amazing spaces and sustainable real estate solutions for our clients, our people and our communities. As a Fortune 500 company, we help real estate owners, occupiers and investors achieve their business ambitions. We have operations in over 80 countries and a global workforce of over 92,000 individuals. We believe a diverse and inclusive culture is one where everyone succeeds. That’s why we’re committed to creating an environment where we all feel welcomed, valued and empowered to achieve our full potential. Confidence can sometimes hold us back from applying for a job. But we’ll let you in on a secret: there’s no such thing as a “perfect” candidate. JLL is a place where everyone can grow no matter how they identify or what background they bring with them. If you’re a leader of any level or experience and this job description resonates with you, let’s talk. Responsibilities Monitor Building Automation Systems (BAS), HVAC, utility, environmental monitoring, and critical fac

JLL empowers you to shape a brighter way . Our people at JLL are shaping the future of real estate for a better world by combining world class services, advisory and technology for our clients. We are committed to hiring the best, most talented people and empowering them to thrive, grow meaningful careers and to find a place where they belong. Whether you’ve got deep experience in commercial real estate, skilled trades or technology, or you’re looking to apply your relevant experience to a new industry, join our team as we help shape a brighter way forward. About JLL- We’re JLL—a leading professional services and investment management firm specializing in real estate. We shape the future of real estate for a better world by using the most advanced technology to create rewarding opportunities, amazing spaces and sustainable real estate solutions for our clients, our people and our communities. As a Fortune 500 company, we help real estate owners, occupiers and investors achieve their business ambitions. We have operations in over 80 countries and a global workforce of over 92,000 individuals. We believe a diverse and inclusive culture is one where everyone succeeds. That’s why we’re committed to creating an environment where we all feel welcomed, valued and empowered to achieve our full potential. Confidence can sometimes hold us back from applying for a job. But we’ll let you in on a secret: there’s no such thing as a “perfect” candidate. JLL is a place where everyone can grow no matter how they identify or what background they bring with them. If you’re a leader of any level or experience and this job description resonates with you, let’s talk. Responsibilities Provide technical leadership and oversight for all building engineering operations, ensuring safe, reliable, and complian

JLL empowers you to shape a brighter way . Our people at JLL are shaping the future of real estate for a better world by combining world class services, advisory and technology for our clients. We are committed to hiring the best, most talented people and empowering them to thrive, grow meaningful careers and to find a place where they belong. Whether you’ve got deep experience in commercial real estate, skilled trades or technology, or you’re looking to apply your relevant experience to a new industry, join our team as we help shape a brighter way forward. About JLL- We’re JLL—a leading professional services and investment management firm specializing in real estate. We shape the future of real estate for a better world by using the most advanced technology to create rewarding opportunities, amazing spaces and sustainable real estate solutions for our clients, our people and our communities. As a Fortune 500 company, we help real estate owners, occupiers and investors achieve their business ambitions. We have operations in over 80 countries and a global workforce of over 92,000 individuals. We believe a diverse and inclusive culture is one where everyone succeeds. That’s why we’re committed to creating an environment where we all feel welcomed, valued and empowered to achieve our full potential. Confidence can sometimes hold us back from applying for a job. But we’ll let you in on a secret: there’s no such thing as a “perfect” candidate. JLL is a place where everyone can grow no matter how they identify or what background they bring with them. If you’re a leader of any level or experience and this job description resonates with you, let’s talk. Responsibilities Coordinate and schedule vendor-performed maintenance, repair, testing, inspections, and project work

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are building innovative physical design capabilities that help bring advanced semiconductor products from concept to silicon. Our team collaborates across design, verification, and manufacturing disciplines to deliver high-quality solutions using leading-edge technologies. We value technical excellence, continuous learning, and a culture of teamwork and innovation. As a Physical Design Engineer, you will play a key role in driving semicustom physical implementation from netlist handoff through tapeout. You will work closely with cross-functional engineering teams to optimize design quality, achieve physical signoff, and support successful product delivery in advanced technology nodes. Responsibilities: Execute the semi-custom physical design flow from netlist handoff through physical verification and tapeout Develop and maintain floorplans, placement, routing, power distribution networks (PDN), and physical design constraints Perform DRC, LVS, parasitic extraction, and physical signoff activities Analyze and resolve timing, signal integrity, electromigration, IR drop, reliability, and manufacturability issues Partner with cross-functional teams to drive design closure, debug issues, and support tapeout readiness Minimum Qualifications: Bachelor's or Master's degree in Electrical Engineering or a related field Experience in VLSI physical design, semiconductor lay

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description The HBM Architecture team develops advanced datapath solutions that enable industry‑leading bandwidth, power efficiency, reliability, and scalability for Micron’s next‑generation High Bandwidth Memory (HBM) products. The team collaborates closely across design, PHY, ECC, verification, layout, and system groups to drive innovative logic‑die and core‑die architectures from concept through production. We are seeking a highly motivated HBM Datapath Architect to architect, design, and optimize high‑speed data paths for next‑generation High Bandwidth Memory (HBM) products! This role focuses on logic‑die and core‑die datapath circuitry, enabling industry‑leading bandwidth, power efficiency, reliability, and scalability across JEDEC and custom HBM solutions. The ideal candidate will work closely with design, PHY, ECC, verification, layout, and system teams to deliver robust datapath designs from concept through silicon bring‑up and production. Responsibilities will include, but are not limited to: Architect and design HBM read and write datapath across core and logic die, including alignment, buffering, timing, and control logic Develop high‑speed, low‑latency datapath circuits supporting multi‑channel HBM architectures and wide internal buses Optimize datapath designs for bandwidth, power, area, and timing closure at advanced technology nodes

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Technical Execution & PI Ownership Lead day‑to‑day Process Integration execution for assigned DRAM modules within the Advanced Technology & Engineering (ATE) organization. Own yield ramp, stability, and integration readiness for assigned scope during technology transfer, pilot, and early HVM phases. Drive root cause investigations for top yield detractors using DOE, SPC/FDC, FMEA, 8D, and structured problem‑solving methodologies. Ensure process window margin, manufacturability, and reliability requirements are met and sustained. Champion adoption of Best‑Known Methods (BKM) and site‑to‑site learning to reduce variability and accelerate learning cycles. Technology Transfer & Ramp Support Execute DRAM technology transfer activities from TD or donor fabs to ID1 under guidance from M2/M3 leadership. Support new product introduction (NPI), process qualification, and customer ramp readiness. Coordinate inter‑fab learning reviews, gap assessments, and corrective action follow‑through. Support extended international assignments (3+ months) for training and technology transfer as required. People Leadership & Coaching Manage and develop a team of Process Integration engineers (NCG and experienced). Provide technical guidance, mentoring, and coaching on PI fundamentals, module ownership, and execution rigor. Set clear priorities, exp

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Be part of a highly skilled and challenging high-speed PHY design team working on advanced technology nodes (12nm and below). Own analog sub-blocks within the PHY and drive specification, design, simulation, reliability, and mixed-mode verification. Leverage AI-enabled tools to improve productivity and decision-making. Drive layout implementation through mask designers while ensuring compliance with process rules and DFM requirements. Participate in design reviews with internal teams and customers, explaining design choices and robustness. Collaborate with cross-functional teams across multiple global locations. Create IP EDA views including Behavioral models, Verilog-A, timing views, and abstracts. Participate in silicon bring-up, characterization, and correlation of silicon results with models and simulations. Mentor and guide junior engineers. Competitive compensation and equal opportunity workplace. Required Skills Strong analog/mixed-signal CMOS circuit design experience in deep sub-micron technologies (2nm to 28nm). Experience in High-Speed Memory Interfaces (DDR3/4/5, LPDDR5/6, GDDR5/6/7) or SerDes Interfaces (PCIe, MIPI, HDMI, USB, SATA, etc.). Full ownership experience of at least one critical PHY sub-block such as: PLL DLL CDR High-speed Receiver with Equalization Transmitter Front-End High-Speed Data Path </ul

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal Physical Design Engineer-DPG-LPDDR at Micron, you will work on innovative memory and storage solutions. These solutions help transform data into intelligence quickly. You will join a dedicated team collaborating to develop world-class products that set industry standards. Key Responsibilities Lead end-to-end RTL-to-GDSII implementation for complex SoCs across advanced technology nodes. Drive floor planning, power planning, CTS, place & route, timing closure, and physical signoff. Own PPA optimization, low-power implementation, congestion management, and design convergence. Lead STA, SI, EM/IR, DRC, LVS, and reliability closure to achieve tape out readiness. Define physical design methodologies, automation strategies, and flow improvements. Partner with Architecture, RTL, DFT, Verification, CAD, and Product Engineering teams to resolve complex implementation challenges. Provide technical leadership, mentor engineers, and drive execution across global teams. Hands-on custom layout design experience is a strong value-added skill, enabling analog/mixed-signal integration, layout optimization, and advanced-node design challenges Leverage Artificial Intelligence (AI) tools to improve RTL-to-GDSII design productivity, quality, and turnaround time. Drive adoption of Generative AI and Agentic AI solutions for physical design automation, design closure, and engineering workflow optimization. <p

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Technical Execution & PI Ownership Lead day‑to‑day Process Integration execution for assigned DRAM modules within the Advanced Technology & Engineering (ATE) organization. Own yield ramp, stability, and integration readiness for assigned scope during technology transfer, pilot, and early HVM phases. Drive root cause investigations for top yield detractors using DOE, SPC/FDC, FMEA, 8D, and structured problem‑solving methodologies. Ensure process window margin, manufacturability, and reliability requirements are met and sustained. Champion adoption of Best‑Known Methods (BKM) and site‑to‑site learning to reduce variability and accelerate learning cycles. Technology Transfer & Ramp Support Execute DRAM technology transfer activities from TD or donor fabs to ID1 under guidance from M2/M3 leadership. Support new product introduction (NPI), process qualification, and customer ramp readiness. Coordinate inter‑fab learning reviews, gap assessments, and corrective action follow‑through. Support extended international assignments (3&#43; months) for training and technology transfer as required. People Leadership & Coaching Manage and develop a team of Process Integration engineers (NCG and experienced). Provide technical guidance, mentoring, and coaching on PI fundamentals, module ownership, and execution rigor. Set clear priorities, expectations, and deliverables aligned with ramp milestones and fab n

At Secureframe , we are not just a company; we are at the forefront of revolutionizing cybersecurity compliance. Recognized as one of the industry's most innovative and trusted providers, Secureframe has consistently received accolades for our advanced technology solutions and commitment to excellence. With a robust portfolio of products that safeguard thousands of businesses worldwide, we have been featured in major publications such as Forbes’ next billion dollar startups , TechCrunch, and The Wall Street Journal for our transformative impact on the way companies achieve and maintain compliance standards. As we continue to grow, our mission remains clear: to provide seamless, secure compliance solutions that enable businesses to focus on what they do best. Joining Secureframe means becoming part of a dynamic team dedicated to professional excellence and continuous learning in an environment that values creativity and forward-thinking. Secureframe is backed by top VCs including Kleiner Perkins, Accomplice, Gradient Ventures (Google’s AI Fund), BoxGroup, Village Global, and many more. About the Implementation Team The Implementation team sits within Secureframe's customer organization and works closely with Sales, Customer Success, Product, Engineering, Security, Support, and our partner ecosystem. This team is responsible for helping customers move from signed contract to real operational readiness: scoped environments, configured platform workflows, clear control ownership, evidence collection, remediation tracking, and a credible path to CMMC assessment. This is an early role on a team we are building from scratch. The right person is not only comfortable delivering customer implementations; they want to help define what excellent CMMC implementation looks like at Secureframe. You will create playbooks, improve handoffs, identify repeatable delivery patterns, pressure-test service packaging, and help turn early customer engagements into a scalable implementation

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal Design Engineer, you will build the future of memory by architecting and delivering high‑performance DRAM circuit compositions for advanced technology nodes. In this highly visible technical leadership role, you’ll develop innovation across building, layout, verification, and silicon validation. You will collaborate closely with multi-functional teams to deliver scalable, manufacturable solutions for next-generation memory products. Your work will directly influence performance, power, reliability, and time‑to‑market for Micron’s groundbreaking memory technologies. Responsibilities Design and optimize DRAM circuits spanning digital, analog, and memory core subsystems to meet aggressive power, performance, and reliability targets Develop and refine floorplans, routing strategies, power delivery networks, sense margins, timings, and die‑size tradeoffs Perform advanced circuit simulations using FINESIM, HSPICE, and VERILOG, analyzing speed, power, noise, and long‑term reliability Model parasitics, verify power and signal integrity, and support validation, reticle experiments, and tape‑out revisions Drive simulation‑to‑silicon correlation, identify gaps, and recommend schematic and layout improvements Lead technical reviews, documentation, and best‑practice standardization across design and layout teams Coordinate and manage layout and build resources, tracking breakthroughs and resolving critical path issues S

At Secureframe , we are not just a company; we are at the forefront of revolutionizing cybersecurity compliance. Recognized as one of the industry's most innovative and trusted providers, Secureframe has consistently received accolades for our advanced technology solutions and commitment to excellence. With a robust portfolio of products that safeguard thousands of businesses worldwide, we have been featured in major publications such as Forbes’ next billion dollar startups , TechCrunch, and The Wall Street Journal for our transformative impact on the way companies achieve and maintain compliance standards. As we continue to grow, our mission remains clear: to provide seamless, secure solutions that enable businesses to focus on what they do best. Joining Secureframe means becoming part of a team dedicated to professional excellence and continuous learning in an environment that values creativity and forward-thinking. Secureframe is backed by top VCs including Kleiner Perkins, Accomplice, Gradient Ventures (Google’s AI Fund), BoxGroup, Village Global, and many more. Join Secureframe's Engineering team and help shape the future of compliance automation. Secureframe highly values having employees working in-office to foster a collaborative work environment and company culture. For office-based employees (employees who live within a defined radius of a Secureframe office), Secureframe considers working in the office, approximately 30% of the time under current policy, to be an essential function of the employee's role. Benefits Medical, dental, and vision benefits for you and your dependent(s) Flexible PTO 401(k) Paid family leave Ground floor opportunity as an early member of the team What you'll do ... Lead technical scoping, design, and implementation of new end-to-end functionality Perform detailed code reviews and provide technical mentorship to engineers Lead architecture and architectural discussions for core parts of the Secureframe application Own multi-team c