Cpu Floorplan Lead Jobs

About the Team OpenAI's Industrial Compute organization is building the world's most advanced AI infrastructure ecosystem. Through a combination of strategic partnerships and self-built campuses, we are scaling the compute, storage, and networking platforms that power frontier AI training and inference. The Scaling Analytics team builds the data and software systems that help Industrial Compute understand, plan, and operate infrastructure at global scale. We work across capacity, hardware, storage, infrastructure software, and operational systems to connect fragmented sources of infrastructure data and make that information reliable and usable for engineering and planning. As OpenAI's infrastructure footprint grows, CPU and storage data increasingly spans internal platforms, vendor systems, APIs, databases, object storage, capacity management systems, and operational tooling. Building reliable connections across these environments is critical to understanding available capacity, utilization, fleet state, and infrastructure growth. About the Role We are seeking a Data Engineer to build the data systems and integrations that connect OpenAI's CPU, storage, and supporting infrastructure platforms. This role sits at the intersection of data engineering and backend software engineering. Rather than focusing primarily on traditional analytical pipelines, you will build the software and integrations required to collect, normalize, and make infrastructure data available across a heterogeneous set of systems. CPU and storage data may originate from internal infrastructure platforms, vendor APIs, databases, object storage, capacity systems, and operational services. You will determine how to reliably connect these systems and where those integrations should live—whether within an existing infrastructure service, an orchestration framework, a scheduled workload, or a purpose-built application. You will work closely with Infrastructure Engineering, Capacity Engineering, Storage,

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team to define and implement RTL for high-performance CPUs. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experienced in CPU microarchitecture with expertise in Rename, Scheduler, ROB, Load Store, Branch Prediction, Cache or Datapath. Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis. Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments. Background in microarchitecture definition, design specification, and performance-driven trade-off analysis. What We Need Own RTL design and microarchitecture development for a portion of a CPU block of a high-performance RISC-V CPU. Collaborate closely with DV, PD, and performance engineers to meet functional, timing, and power goals. Use innovative techniques to optimize power, performance, and

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a Design Verification Engineer to contribute to the unit-level verification of our RISC-V CPU front end—including instruction fetch, branch prediction, and surrounding fetch control structures. As a key individual contributor within our front-end DV team, you will focus on building testbenches, generating stimulus, and developing checkers for complex microarchitectural scenarios. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Front-End Experience: Solid background verifying CPU front-end blocks—such as instruction fetch, branch predictors (BTB, TAGE, RAS), instruction caches/TLBs, or decode—using SystemVerilog, UVM, and C++. Unit-Level Focus: Hands-on experience building clean, controllable unit testbench environments with precise stimulus and checking. Reusable Design: Pragmatic approach to building transactors, predictors, and scoreboards that can be reused across verification levels. Collaborative Problem Solver: Comfortable working alongside RTL designers to trace and fix misspeculation, redirect, and edge-case fetch bugs. What We Need Unit-Level Verifica

... Facility: CPU BANGALORE Job Code: IJP567296 | Source: Sodexo India

... Facility: CPU HYDERABAD Qualification: 12th Job Code: IJP567208 | Source: Sodexo India

... Facility: CPU HYDERABAD Qualification: 12th Job Code: IJP567213 | Source: Sodexo India

... Facility: CPU HYDERABAD Qualification: 12th Preferred Gender: FEMALE Job Code: IJP567209 | Source: Sodexo India

... Facility: CPU HYDERABAD Qualification: 12th Job Code: IJP567201 | Source: Sodexo India

... Facility: CPU BANGALORE Job Code: IJP558429 | Source: Sodexo India

... Facility: CPU HYDERABAD Qualification: 12th Job Code: IJP561988 | Source: Sodexo India

... Facility: CPU BANGALORE Job Code: IJP563368 | Source: Sodexo India

... Facility: CPU BANGALORE Job Code: IJP563746 | Source: Sodexo India

... Facility: CPU BANGALORE Job Code: IJP563793 | Source: Sodexo India

... Facility: CPU HYDERABAD Qualification: 12th Job Code: IJP565512 | Source: Sodexo India

... Facility: CPU PUNE Qualification: Diploma Job Code: IJP566792 | Source: Sodexo India